- Cisco (Portland, OR)
- ASIC DFT Product Lead Apply (https://jobs.cisco.com/jobs/Login?projectId=1435540) + Location:Portland, Oregon, US + Alternate LocationPortland, OR, USA + Area of ... **Your Impact** : You will be in the Silicon One development organization as an ASIC DFT Product Lead in San Jose, CA with a primary focus on Design-for-Test and… more
- Cisco (San Jose, CA)
- …Masters +4 years of related experience, or PHD + 1 years of experience in ASIC DFT flows and implementation. + Prior experience implementing scan control logic ... ASIC DESIGN FOR TEST ENGINEER - Acacia Apply...Scan/ATPG & MBIST/Repair/Fuse. + You will work with seasoned DFT engineers to implement and verify Design For Test.… more
- Broadcom (Fort Collins, CO)
- …have a Candidate Account, please Sign-In before you apply.** **Job Description:** DFT Quality Engineer Broadcom's ASIC Product Division is seeking candidates ... our products through Research & Development of comprehensive Design for Test ( DFT ) structures, patterns & test strategies. You will work collaboratively with… more
- Qualcomm (San Diego, CA)
- …performance, and area of the IPs - Assist in running the full suite of front-end ASIC design tools (lint checking, CDC, DFT , synthesis, FV, STA, etc.) - Develop ... **General Summary:** Qualcomm mixed-signal IP design team is seeking talented senior ASIC digital designers to join our efforts in developing the next generation… more
- NVIDIA (Santa Clara, CA)
- …DDR or related protocols. + You have experience with all stages in the ASIC design flow including emulation, prototyping, DFT , timing analysis, floor planning, ... We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers to design… more
- NVIDIA (Santa Clara, CA)
- …yield enhancement and spec validation + Partner with other engineering groups including ASIC , DFT , ATE, silicon validation, fab process, software and quality ... teams to coordinate efforts and resolve silicon issues + Initiate and drive process improvements/preventative actions through root cause analysis + The ideal candidate will always look to improve workflows, products, functions and methodologies while working… more
- Google (Mountain View, CA)
- …Debug/Trace, Interrupts, Clocks/Reset. + Knowledge of FPGA and emulation platforms. + Knowledge of ASIC Verification or DFT . Be part of a team that pushes ... in Electrical Engineering, Computer Engineering or Computer Science. + Experience with ASIC design methodologies for clock domain checks, reset checks and low power… more
- Qualcomm (San Diego, CA)
- …transformation to help create a smarter, connected future for all. The Digital ASIC Design Team is currently seeking candidates who will be responsible for the ... implementation and verification of advanced DFT /DFD (Design for Test/Design for Debug) techniques for low...Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.… more
- Cadence Design Systems, Inc. (Cary, NC)
- …who want to make an impact on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate ... testbenches. + Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test... Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT… more
- Palo Alto Networks (Santa Clara, CA)
- …all win with precision. **Your Career** We are looking for a Senior Director of ASIC Engineering to manage and lead a high performing ASIC and FPGA development ... and silicon development experience, and a proven track record of first-pass success in ASIC , FPGA and Systems. **Your Impact** + The Director of ASIC /FPGA will… more