- Cisco (San Jose, CA)
- …the industry. Your Impact: You will be in the Silicon One development organization as an ASIC DFT Product Lead in San Jose, CA with a primary focus on ... activities Key Responsibilities: * Responsible for implementing the Hardware Design-for-Test ( DFT ) features that support ATE, in-system test, debug and diagnostics… more
- Cisco (San Jose, CA)
- …Work With: You will be in the Silicon One development organization as a senior DFT verification lead in San Jose, CA. You will work with Front-end RTL teams, backend ... physical design teams to understand chip architecture and drive high-quality DFT verification. What You'll Do: * Responsible for thorough test planning and… more
- Qualcomm (Santa Clara, CA)
- …in digital ASIC design; experience using Verilog or VHDL + Experience with ASIC test, DFT , and debug + 6+ years of practical experience with test ... create a smarter, connected future for all. As a DFT Engineer you will work with chip architects, chip...designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and… more
- Cisco (Maynard, MA)
- …with + 6 years of experience, or PHD with + 3 years of experience in ASIC DFT flows and Implementation * Prior experience implementing scan control logic in RTL ... ultra-long haul telecommunication networks. This role is within our ASIC team, specifically as part of the Design for...Scan/ATPG & MBIST/Repair/Fuse. * You will work with seasoned DFT engineers to implement and verify DFT .… more
- Cisco (San Jose, CA)
- …Your Impact: You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. Key Responsibilities: * Responsible for… more
- Amazon (Sunnyvale, CA)
- …both logic and physical synthesis flow for various technology nodes. * Work with the ASIC design and DFT teams to understand the design and create timing ... or equivalent experience. * 7+ years of experience in ASIC implementation, ie, synthesis, STA and working with P&R.../ Communications Engineering. * 10+ years of experience in ASIC implementation. * Experience in leading physical design. *… more
- Qualcomm (San Diego, CA)
- …performance, and area of the IPs - Assist in running the full suite of front-end ASIC design tools (lint checking, CDC, DFT , synthesis, FV, STA, etc.) - Develop ... **General Summary:** Qualcomm mixed-signal IP design team is seeking talented senior ASIC digital designers to join our efforts in developing the next generation… more
- Cisco (San Jose, CA)
- …industry. Who You'll Work With You will work with outstanding talent and vast ASIC development expertise in design, DV, DFT , physical design, and post-silicon ... a system company, so you can also use the ASIC to work with the System and Software teams...What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. *… more
- NVIDIA (Santa Clara, CA)
- …of DRAM controllers is a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT , timing analysis, floor planning, ECO, ... NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of hard-working… more
- NVIDIA (Santa Clara, CA)
- …DDR or related protocols. + You have experience with all stages in the ASIC design flow including emulation, prototyping, DFT , timing analysis, floor planning, ... We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers to design… more
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