- Northrop Grumman (Morrisville, NC)
- …they're making history. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking an ASIC DFT Engineer to join our team of highly qualified, ... DoD Secret clearance.** **Roles and Responsibilities:** + Responsible for DFT (Design for Testabilty) aspects of ASIC ...for DFT (Design for Testabilty) aspects of ASIC Design thorough understanding of digital design concepts +… more
- Meta (Sunnyvale, CA)
- … DFT EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer , DFT Responsibilities: 1. Develop and implement DFT ... **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and… more
- Google (Mountain View, CA)
- …related field, or equivalent practical experience. + 8 years of experience in DFT or physical design. + Experience with scan insertion, Automatic Test Pattern ... (JTAG), Internal JTAG (IJTAG) tools and flow. + Experience with DFT Electronic Design Automation (EDA) Tools like Tessent/Genus/FC/Simvision, etc. **Preferred… more
- Amazon (Austin, TX)
- …Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test ( DFT ) architectures * Work with block designers to integrate DFT ... Work with physical design team to setup and implement DFT insertion flow * Develop high coverage and cost...insertion flow * Develop high coverage and cost effective DFT methodologies * Perform RTL coding and Verification *… more
- Cadence Design Systems, Inc. (Cary, NC)
- …on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and ... testbenches. + Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test... Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT… more
- Broadcom (San Jose, CA)
- …switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. . You ... you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...CMOS analog circuit and physical design + Knowledge of DFT /Scan/MBIST/LBIST and understanding of their impact on physical design… more
- SpaceX (Bastrop, TX)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...CMOS analog circuit and physical design + Knowledge of DFT /Scan/MBIST/LBIST and understanding of their impact on physical design… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We...with the Designers to create waivers 6. Perform RTL DFT Analysis and improve the DFT coverage… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you ... intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL...power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure functional and timing… more