- Cisco (San Jose, CA)
- …of engineers to complete verification of a complex block, cluster or chip-level design * Lead verification for a complete SOC or ASIC i * Prior Experience with ... working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact: You will gain...You will: * Architect block, cluster and top level DV environment infrastructure * Create DV infrastructure… more
- Qualcomm (Santa Clara, CA)
- …milestone planning & critical debugs + Build, manage and mentor a team of ASIC DV engineers + Explore innovative DV methodologies (formal, simulation, ... As a Design Verification Lead , you will lead a team of ASIC design verification...plus + 8+ years or more of practical semiconductor ASIC DV experience including owning end-to-end verification… more
Locations:
California