- Meta (Jefferson City, MO)
- **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide… more
- Amazon (Austin, TX)
- …be responsible for defining and checking the specification of critical hardware modules using formal methods and industrial model checkers. You will be a part of a ... 2022 and September 2025. * Completed coursework or prior internship experience with formal methods (SW/HW) * Coursework or prior internship experience in the basics… more
- Lockheed Martin (Denver, CO)
- **Description:** Join Our Team as an ** ASIC & FPGA Lead Verification Engineer ** where you will support over 50 different programs and research and ... world, and are seeking a highly talented and motivated ** ASIC & FPGA Verification Engineer **...test pattern generation, logic equivalency checking, linting and/or other formal design checks\. * Knowledge of space\-grade/qualified FPGAs and… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 20.… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
- Qualcomm (San Diego, CA)
- …such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware ... closely related field + 2+ years of experience with ASIC design and verification tools, techniques, and...as UVM or OVM and exposure to Assertion based Formal Verification + 3+ years of experience… more
- Cisco (San Jose, CA)
- ASIC Verification Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431425) + Location:San Jose, California, US + Area of InterestEngineer - ... Verilog / UVM programming + 4+ Years post graduate ASIC Verification processes, methodologies, flows and tools...Understanding of Networking technologies and concepts + Experience with Formal verification + Experience with Post-silicon lab… more
- Cisco (San Jose, CA)
- ASIC Design Verification Engineer Apply...MMU. + Experience with Veloce/HAPS is a plus + Formal verification (iev/vc formal ) knowledge is ... Work With:** You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with … more
- Qualcomm (San Diego, CA)
- …that meet performance, security, technology, and feature requirements. As a Design Verification Engineer , you will work with Chip Architects to validate ... smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer , you will plan, design,...Science, Engineering, or related field and 4+ years of ASIC design, verification , validation, integration, or related… more
- Cisco (San Jose, CA)
- Senior ASIC Design Verification Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1444077) + Location:San Jose, California, US + Area of ... in the industry. **Your Impact** + Participate in the ASIC design verification for Cisco high-end switching...and/or Python/Perl. + Experience in Networking. + Experience with Formal verification . **Why Cisco?** At Cisco, we're… more
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