- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing,… more
- NVIDIA (Santa Clara, CA)
- …life's work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic...with Static Timing Analysis (STA) + Experience physical design and optimization eg, synthesis, floorplanning,… more
- Cisco (San Jose, CA)
- …teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this ... startup-style team. You'll collaborate with exceptional talent with deep ASIC design and development expertise. As part...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing… more
- Northrop Grumman (Linthicum Heights, MD)
- …+ Work closely with design , verification, design -for-test and physical design teams to optimize the timing and improve design performance + ... maintain timing methodologies and flows for efficient timing analysis and closure + Conduct design ...of experience in the full product life cycle of ASIC Design **Preferred Qualifications:** + Master's Degree… more
- NVIDIA (Westford, MA)
- …to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking ... in a technology-focused company. What you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block… more
- Northrop Grumman (Jessup, MD)
- …Verilog, System Verilog or VHDL RTL + Circuit synthesis, formal verification, and static timing using state-of-the-art digital ASIC design tools + Developing ... advantages to the warfighter. We are seeking a front-end ASIC design engineer for design ...engineers for floor planning and clock tree constraints and timing closure. Automated place and route and physical… more
- SpaceX (Irvine, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- SpaceX (Bastrop, TX)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- The Boeing Company (Mountain View, CA)
- …and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate ... & Weapons Systems has an exciting opportunity for multiple ** ASIC and/or FPGA Design and Verification Engineers**...team and third-party IP as needed + Perform static timing analysis, LEC, CDC, linting, and other necessary checks… more
- Meta (Austin, TX)
- **Summary:** Join Meta's Infrastructure organization to leverage your expertise in ASIC Physical Design , driving high-performance, AI/ML SoC and IP ... and innovation of our data center applications. **Required Skills:** ASIC Engineer Physical Design Responsibilities:...equivalent practical experience 10. 8+ years of experience in physical design and timing closure… more
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