- SpaceX (Sunnyvale, CA)
- Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building… more
- Broadcom (Fort Collins, CO)
- …exceeding 1 GHz, from concept through production. **Role Overview** This Floorplanning Engineer role focuses on chip -level physical architecture and integration ... for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes, defining and optimizing the overall die layout, including partitioning, hierarchy, and placement of major functional… more
- Broadcom (San Jose, CA)
- …candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network switch/routing designs. The day-to-day ... 1). Defining in the microarchitecture and implementing design of chip top level modules for L2/L3 Network Switching and...ASICs and various subsystems within these chips. 2). Doing chip level integration and putting all the functional blocks,… more
- Global Foundries (Malta, NY)
- …information, visit www.gf.com . Summary of Role: This hands-on Package and chip assembly Engineering role will develop industry leading advanced packaging utilizing ... required - Wafer level processing for TSV's, RDL, and bumping, advanced flip chip on chip and chip on wafer assembly, Wafer singulation, and chip… more
- Broadcom (Fort Collins, CO)
- …**Job Description:** **You will fit this role if:** + You are an expert in full- chip power integrity analysis using state of the art tools that are able to parallel ... level through PDN simulations **More specifically we are looking for a chip power integrity expert with the following hands-on know-how:** + Developed innovative… more
- NVIDIA (Santa Clara, CA)
- …and verification of architectural, rtl, and gate level designs. As a software engineer , you will craft highly efficient software to automate and facilitate chip ... Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages...+ Optimize the daily workflows of the world's top chip modelers and designers. What We Need to See:… more
- NVIDIA (Santa Clara, CA)
- We are looking to hire a Chip Design Verification Engineer to join NVIDIA Chip Design group. The work environment is versatile, educational, dynamic and ... the world's most advanced AI data centers. We are seeking a senior verification engineer to help us ensure the quality and correctness of this critical technology.… more
- Meta (Sunnyvale, CA)
- …teams (ie, architecture, Intellectual Property, Firmware, Electrical Engineering, System on Chip , and product engineer teams) to generate validation reports ... content. The Reality Labs team seeks a Silicon Validation Engineer .As a Silicon Validation Engineer , you will..., Reality Labs Responsibilities: 1. Responsible for System on Chip and end-to-end system validation plan development, execution and… more
- Global Foundries (Richardson, TX)
- …For more information, visit www.gf.com. Summary of Role: Seeking a Senior System-on- Chip Design Verification engineer to verify the High-Performance Data ... Processing Unit Chiplets and Automotive Microcontrollers . The candidate will be responsible for contributing to all phases of the verification life cycle, including reviewing specifications, developing testbench architecture, creating testplans , defining and… more
- Google (Sunnyvale, CA)
- …architecture and its integration within AI/ML-driven systems. As a System on a Chip (SoC) Physical Design Engineer , you will collaborate with Register-Transfer ... SoC Physical Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid**...Level (RTL), Design for Testing (DFT), Floorplan, and full- chip Sign off teams. Additionally, you will solve technical… more
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