• CMOS Device Integration…

    Micron Technology, Inc. (Boise, ID)
    …inspiring the world to learn, communicate and advance faster than ever. As an Advanced CMOS Device & Process Integration Engineer , you will play a crucial ... 10+ years of experience in developing FinFET and/or industry experience in CMOS device technology and process integration + Knowledge of Nano sheet and vertical… more
    Micron Technology, Inc. (06/12/25)
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  • CMOS Device and Memory…

    Google (San Diego, CA)
    …embedded SRAM design (cell and macro) and characterization. + Experience in CMOS technology and device characterization, process integration and SPICE ... simulation. + Experience with investigative analysis and investigative tools such as JMP, spreadsheets. Preferred qualifications: + Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related… more
    Google (06/21/25)
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  • Sr Engineer Device Engineering

    Global Foundries (Malta, NY)
    …markets. For more information, visit www.gf.com . Summary of Role: As a silicon photonics device engineer , you will be working on the development of CMOS ... engineering physical science discipline. + Background in photonics, photonic device physics, CMOS device physics, semiconductor processing, and photonic … more
    Global Foundries (04/29/25)
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  • Staff Device Engineer

    Takeda Pharmaceuticals (Lexington, MA)
    …to the best of my knowledge. **Job Description** **Primary** **Role:** The Staff Device Engineer will lead technical efforts for combination products and drug ... functional team to support lifecycle management of commercial combination product. The Staff Device Engineer has extensive experience in medical devices for drug… more
    Takeda Pharmaceuticals (05/02/25)
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  • Device Technology Reliability…

    onsemi (Gresham, OR)
    ** Device Technology Reliability Engineer ** This engineering position for development unique tests for CMOS or SiC technology is located at Scottsdale, AZ, ... with Wafer Level Reliability programs for power devices, advanced CMOS , DMOS devices, SiC or related technologies. You will...of test equipment. **REQUIREMENTS:** + _Experience with SiC or CMOS gate oxide process reliability_ + Strong knowledge of… more
    onsemi (05/23/25)
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  • Experienced RF Device Modeling Lead - PMTS

    Global Foundries (Essex Junction, VT)
    …visit www.gf.com. Summary of Role: This position is for an experienced RF Device Compact Modeling Engineer . The candidate will be responsible for transistor ... strategy and customer acceptance. + Good understanding of the device physics of SOI and bulk CMOS RF transistors and the correlation of the process technologies… more
    Global Foundries (06/26/25)
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  • RFIC Design Engineer

    Skyworks (Cedar Rapids, IA)
    RFIC Design Engineer Apply now " Date:May 30, 2025 Location: Cedar Rapids, IA, US Company: Skyworks If you are looking for a challenging and exciting career in the ... and utilize a broad range of technologies (SOI, silicon CMOS , GaAs, IPD, TC-SAW and pHEMT) to create differentiated...or SOI RFIC design. He/she must understand the basic device physics, have the ability to develop and use… more
    Skyworks (05/31/25)
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  • Electronic-Photonic Process Design Kit (PDK)…

    MIT Lincoln Laboratory (Lexington, MA)
    …computing, radiation-hard CMOS , and other emerging integrated circuit technologies. The engineer will work in the Cadence environment, with which they should be ... including development of bulk and epitaxial crystal growth, charge-coupled device (CCD) imagers, 193-nm lithography, fully depleted silicon-on-insulator (FDSOI) … more
    MIT Lincoln Laboratory (05/09/25)
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  • Integrated Circuit (IC) Layout and Mask Design…

    MIT Lincoln Laboratory (Lexington, MA)
    …computing, radiation-hard CMOS , and other emerging integrated circuit technologies. The engineer will work in the Cadence environment, with which they should be ... including development of bulk and epitaxial crystal growth, charge-coupled device (CCD) imagers, 193-nm lithography, fully depleted silicon-on-insulator (FDSOI) … more
    MIT Lincoln Laboratory (05/29/25)
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  • Process Integration Engineer III - (E3)

    Applied Materials (Santa Clara, CA)
    Engineer III - (E3) **Preferred skillset and experience:** + Advanced logic CMOS device with semiconductor process flow understanding + Experience working ... 3-5 years working in a fab as module development/integration engineer , or Ph.D. with focus on CMOS Power - Performance improvement including new materials or new… more
    Applied Materials (05/24/25)
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