• Senior Analog Layout Engineer

    Capgemini (San Francisco, CA)
    …digital-to-analog converters, PLL, transceivers, etc. Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated ... **Required Skills** + .10 years' experience in high performance analog layout in advanced CMOS process. + .Experience in IC layout of cutting-edge… more
    Capgemini (06/24/25)
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  • Senior CAD Engineer, Physical Design

    NVIDIA (Santa Clara, CA)
    …5 years industry experience. + Have an in-depth understanding of mosfet device behavior, CMOS layout , and VLSI design. + Experience working with standard cell ... design & layout . + Great interpersonal skills. + A passion for providing excellent support for end-users. NVIDIA offers highly competitive salaries and a… more
    NVIDIA (04/30/25)
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  • CAD Engineer

    NVIDIA (Santa Clara, CA)
    …plus year of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Excellent programming skills; experience with ... perl, Cadence SKILL, C++, tcl. + Great interpersonal skills + Passionate about providing excellent support for end-users. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our… more
    NVIDIA (06/11/25)
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  • Senior CAD Engineer, Custom Circuit Designers

    NVIDIA (Santa Clara, CA)
    …Engineering and 4+ year's experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design + Excellent programming skills + Experience ... with perl, Cadence SKILL, python, tcl + Great communication skills + Passionate about providing excellent support for end-users. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth,… more
    NVIDIA (06/05/25)
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  • CAD Engineer

    NVIDIA (Santa Clara, CA)
    …plus year of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Understanding of version control software ... preferably Perforce. + Understanding the regression testing methodology. + Excellent programming skills; experience with perl, python and other scripting languages. + Great interpersonal skills + Passionate about providing excellent support for end-users.… more
    NVIDIA (06/03/25)
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  • Senior ICV CAD Engineer

    NVIDIA (Santa Clara, CA)
    …5+ years of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Excellent programming skills; experience with ... perl, Cadence SKILL. + Expertise in ICV in order to support, enhance, and debug foundry DRC and LVS techfiles. + Being able to implement NVIDIA specific DFM, DRC rules using ICV. + Add NVIDIA specific devices in the LVS deck using ICV. + Great interpersonal… more
    NVIDIA (06/03/25)
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  • CMOS Device Integration Engineer, MTS

    Micron Technology, Inc. (Boise, ID)
    …the world to learn, communicate and advance faster than ever. As an Advanced CMOS Device & Process Integration Engineer, you will play a crucial role in the ... development of current and future CMOS technology. You will be responsible for device and...with teams across the organization including Process, Circuit, Design, Layout , Product Engineering, and Modeling/TCAD. Your expertise will be… more
    Micron Technology, Inc. (06/12/25)
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  • Senior Mask Layout Design Engineer

    NVIDIA (Santa Clara, CA)
    …integration would be excellent to have. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies + Validated experience with Cadence ... If yes, We are looking for a Senior Mask Layout Design Engineer - someone who is excited to...circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools + You'll work with… more
    NVIDIA (04/13/25)
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  • Sr. Director, Engineering

    Skyworks (Andover, MA)
    …Amplifiers, PMU and Switching regulators + Advanced knowledge of device physics, CMOS fabrication processes, layout tradeoffs for high performance circuits + ... Hands on experience with SOC debug, validation, characterization, test techniques and equipment + Strong knowledge of IC design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc. + Ability to work in a dynamic environment with changing needs and… more
    Skyworks (04/02/25)
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  • Senior Failure Analysis Engineer

    Power Integrations (San Jose, CA)
    …is required. Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required. + Verbal and reading, ... skills in Mandarin is required. + Excellent English speaking, reading and technical writing skill is required. + Candidates with direct experience in customer interface on resolution of customer quality problems will be given special consideration. +… more
    Power Integrations (04/22/25)
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