- Google (Mountain View, CA)
- Senior CPU Physical Design Engineer , Silicon _corporate_fare_ Google _place_ Austin, TX, USA; Mountain View, CA, USA **Mid** Experience driving progress, ... field, or equivalent practical experience. + 5 years of experience with physical design flow such as constraints, synthesis, floor planning, place and route,… more
- NVIDIA (Hillsboro, OR)
- We are looking for a Senior CPU Design Engineer ! NVIDIA is seeking best-in-class CPU Design Engineers to design the world's leading CPUs. This ... will work closely with fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks. What you will be… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible ... network and last-level caches , working closely with the physical design team on implementation, synthesis and...CPU team, you'll be a liaison between Logic design and Physical design teams… more
- NVIDIA (Santa Clara, CA)
- …design the GPU or CPU clocks to satisfy all the architectural/ design / physical constraints. + Improve Power, Performance, and Area (PPA) of innovative ... CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the...implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes + Develop flows for advanced place and route… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes + Develop flows for advanced place and route… more
- Capgemini (Seattle, WA)
- **Job Description:** We are seeking a SoC Design Verification Engineer to join our team 100% onsite in either Seattle, WA or Santa Clara, CA. The ideal candidate ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Lead E/E & Semiconductor Engineer - SOC Design Verification Engineer_ **Location:** _WA-Seattle_… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...+ ASIC/SoC system integration experience + Experience with multicore CPU subsystem design + Experience with standard… more
- Capgemini (Santa Clara, CA)
- **About the Job You're Considering** + Test and bring-up FPGA and CPU based boards and systems + Review system specification documents for architecture, electrical, ... and mechanical requirements + Work closely with in-house board design teams and external contractors to guide and review...digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of… more
- Microsoft Corporation (Hillsboro, OR)
- …Python OR equivalent experience. + 10+ years of relevant experience. + Expertise in CPU /SoC design principles. + For Front-End Handoff CAD Roles: + In-depth ... assurance checks across front-end areas like RTL & VIP Design , Design Verification, Validation, DFT, Emulation, ...silicon solutions for Microsoft. As a Senior Front-End CAD Engineer , you'll drive the development and adoption of cutting-edge… more
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