• Senior Chip - Design Verification…

    NVIDIA (Belfast, ME)
    NVIDIA is looking for a Senior Verification Engineer to join our Networking Chip Design team in Belfast, focusing on products such as our ConnectX Ethernet ... which are revolutionising today's Data Centre. As a Senior Chip - Design Verification Engineer , you will...core units within the Network Adapter and BlueField SoC ( System -on- Chip ) silicon teams + Use advanced verification… more
    NVIDIA (05/21/25)
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  • Physical Design Engineer , Custom…

    Google (Sunnyvale, CA)
    …and its integration within AI/ML-driven systems . As a Custom Datapath Physical Design Engineer on the Chip Implementation team, you will work ... experience. + 10 years of experience in ASIC physical design and methodologies in advanced process nodes. + Experience...your ideas into our flows and designs. The ML, Systems , & Cloud AI (MSCA) organization at Google designs,… more
    Google (06/21/25)
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  • Research Engineer , Chip

    Google (Mountain View, CA)
    …you'll have the opportunity to revolutionise AI by applying state-of-the-art AI to Chip Design . We develop research breakthroughs that impact all aspects of ... develop and apply state-of-the-art AI methods and models to Chip Design and work closely with research...ML models, hardware generation and verification, RTL optimization, and system design . + Engage and work in… more
    Google (05/08/25)
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  • Senior ASIC Full Chip Verification…

    NVIDIA (Austin, TX)
    …levels (eg, unit, sub- system , and SOC). What you'll be doing: + Design and maintain the Full Chip Verification environment. + Understand the architecture ... work, to amplify human inventiveness and intelligence. The NVIDIA System -On- Chip (SOC) group is looking for a...for verification methodologies and implementation that enable high quality system -level IP design and robust verification at… more
    NVIDIA (05/08/25)
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  • Enablement Engineer , On- chip power…

    Qualcomm (San Diego, CA)
    …power delivery. Ideal candidates should have a background in 2.5D/3D on- chip integration, process technology, and design enablement. Responsibilities include: ... has a position in San Diego, CA, focusing on on- chip power grid optimization for sub 2nm nodes. The...for sub 2nm nodes. The role involves driving 3D system integration, balancing performance and cost, and includes responsibilities… more
    Qualcomm (05/22/25)
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  • Lead Product Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …team, product marketing team to influence the development of software tools for advanced chip design platforms. As Product Engineer , you will be a ... MS in EE with 1+ years of experience in Digital Implementation, either as a design engineer or as a product engineer Strong understanding of VLSI physical … more
    Cadence Design Systems, Inc. (05/21/25)
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  • Senior Chip Master Capacity Planner​

    NVIDIA (Santa Clara, CA)
    …exploration, to deep learning in robotics, medicine, computational finance and automotive design . And we've only scratched the surface of what we can accomplish ... What you will be doing: + Lead the implementation of automated planning systems (Anaplan and Ops Data Platform), driving process standardization and team efficiency.… more
    NVIDIA (06/27/25)
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  • Principal / Senior Principal Electromechanical…

    Northrop Grumman (Baltimore, MD)
    …Grumman Mission Systems is seeking a Principal/Senior Principal Electromechanical Design Engineer to join our team of qualified, diverse individuals. ... to less experienced personnel. This position may be filled as a Principal Electromechanical Design Engineer or a Senior Principal Electromechanical Design more
    Northrop Grumman (05/23/25)
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  • Principal Silicon Circuits System

    NVIDIA (Santa Clara, CA)
    …to lead show-stopper bugs to enable product shipment. + Work alongside system architects, chip and board designers, software/firmware engineers, HW/SW ... MS with 13+ years experience in EE, CE, CS, Systems Engineering, or similar and experience in a related...offshore teams preferred. + A background in board PDN design and in-depth knowledge of chip -and board-level… more
    NVIDIA (06/13/25)
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  • Scientist, Space Systems - Phased Array RF…

    L3Harris (Palm Bay, FL)
    …of national security. Job Title: Scientist, Space Systems - Phased Array RF Design Engineer Job Code: 24693 Job Location: Palm Bay, FL Job Description: The ... Design Engineer to lead sophisticated RF/Microwave design activities, leveraging extensive expertise in RF system...such as Integrated Product Team (IPT) Lead or Chief Systems Engineer . #LI-KB1 L3Harris Technologies is proud… more
    L3Harris (06/12/25)
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