• ASIC Engineer, DFT

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and ... are looking for individuals with a background in Design for Testability ( DFT ) methodologies and implementation for IP/SOC, with demonstrated use and understanding of… more
    Meta (08/01/25)
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  • DFT Engineer (eInfochips)

    Arrow Electronics (Santa Clara, CA)
    **Position:** DFT Engineer (eInfochips) **Job Description:** **Position: DFT Engineer** **Location: San Jose CA (Remote)** **Experience: 8+ Years** **What You'll ... Be Doing:** Develop and implement comprehensive DFT architectures tailored to specific design requirements. Design and implement robust DFT infrastructure,… more
    Arrow Electronics (07/29/25)
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  • ASIC DFT Product Lead

    Cisco (Portland, OR)
    ASIC DFT Product Lead Apply (https://jobs.cisco.com/jobs/Login?projectId=1435540) + Location:Portland, Oregon, US + Alternate LocationPortland, OR, USA + Area of ... in the Silicon One development organization as an ASIC DFT Product Lead in San Jose, CA with a...**Key Responsibilities:** + Responsible for implementing the Hardware Design-for-Test ( DFT ) features that support ATE, in-system test, debug and… more
    Cisco (07/05/25)
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  • Lead ASIC DFT Engineer

    Google (Mountain View, CA)
    …related field, or equivalent practical experience. + 8 years of experience in DFT or physical design. + Experience with scan insertion, Automatic Test Pattern ... (JTAG), Internal JTAG (IJTAG) tools and flow. + Experience with DFT Electronic Design Automation (EDA) Tools like Tessent/Genus/FC/Simvision, etc. **Preferred… more
    Google (08/08/25)
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  • DFT Design Engineer, AWS Machine Learning…

    Amazon (Austin, TX)
    …Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test ( DFT ) architectures * Work with block designers to integrate DFT ... Work with physical design team to setup and implement DFT insertion flow * Develop high coverage and cost...insertion flow * Develop high coverage and cost effective DFT methodologies * Perform RTL coding and Verification *… more
    Amazon (08/04/25)
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  • ASIC DFT Engineer I, Annapurna Labs

    Amazon (Austin, TX)
    …Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test ( DFT ) architectures * Work with block designers to integrate DFT ... Work with physical design team to setup and implement DFT insertion flow * Develop high coverage and cost...insertion flow * Develop high coverage and cost effective DFT methodologies * Perform RTL coding and Verification *… more
    Amazon (07/02/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most ... network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. .… more
    Broadcom (08/01/25)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan ... teams to drive scalable, automated solutions. + Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to...field + 5+ years of hands-on experience in Design-For-Test ( DFT ) + Deep knowledge of DFT tools,… more
    NVIDIA (06/17/25)
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  • Sr Principal DFT Application Engineer

    Cadence Design Systems, Inc. (Cary, NC)
    …looking for SoC/ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and experience in scan chain insertion, compression scan ... SoC/ASIC Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT...( DFT ) + Should possess intimate knowledge of DFT insertion flows + Basic scan chain insertion using… more
    Cadence Design Systems, Inc. (06/06/25)
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  • Lead Software Engineer, DFT /Atpg

    Cadence Design Systems, Inc. (Austin, TX)
    …engineer to work with the Modus Test R&D team working on Design For Test ( DFT ) and Automatic Test Pattern Generation (ATPG) Software. What You'll Be Doing + Work as ... worldwide + Develop software tools in C/C++ to support DFT /ATPG + Research and develop software solutions to allow...Out From The Crowd + Experience in VLSI and/or DFT /ATPG. + Experience with multi-threading and distributed software +… more
    Cadence Design Systems, Inc. (07/18/25)
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