- US Tech Solutions (Goleta, CA)
- …independently and take ownership of verification deliverables within a UVM /SystemVerilog environment. + The engineer will collaborate with design, ... **Job Description:** + The Verification Engineer will contribute to the... prior to tape-out. **Responsibilities:** + Perform pre-silicon functional verification of digital designs using UVM and… more
- L3Harris (Columbia, MD)
- …cutting-edge tactical communication systems that protect those who protect us. As an FPGA Verification Engineer , you'll collaborate with a talented, ... Job Title: Senior Specialist, Electrical Engineer - FPGA /ASIC Verification Engineer Job Code:...Programming(C++, JAVA). + Proven proficiency in FPGA /ASIC verification using SystemVerilog. + Working knowledge of UVM… more
- Lockheed Martin (Denver, CO)
- **Description:** Join Our Team as a **ASIC/ FPGA Verification Engineer ** where you will work on the development of a sophisticated state\-of\-the\-art ... are seeking a highly talented and motivated **ASIC & FPGA Verification Engineer ** who has...ASIC/ FPGA verification experience with modern verification methodologies such as UVM , OVM or… more
- The Boeing Company (El Segundo, CA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC/ FPGA Verification Engineer on the Boeing Electronic Products team ... units designed at other sites. **Position Responsibilities:** + Design and implement an ASIC/ FPGA verification environment utilizing UVM & System Verilog. +… more
- BAE Systems (Westminster, CO)
- …Other incentives may be available based on position level and/or job specifics. **Principal FPGA Verification Engineer - $15K Sign On Bonus** **114981BR** ... used across multiple projects. + Work in a System Verilog/ UVM environment developing tests, testbenches, UVM components,...regressions/testlists. + Be responsible for generating and executing the FPGA Verification Test Plan and FPGA… more
- Lockheed Martin (Highlands Ranch, CO)
- **Description:** Join Our Team as a **ASIC/ FPGA Verification Engineer ** where you will work on the development of a sophisticated state\-of\-the\-art ... Space's Silicon Solutions team and seeking a future\-looking Principal Verification Engineer who is able to case...of FPGA and ASIC devices utilizing modern verification methodologies such as UVM \. * Experience… more
- Northrop Grumman (Jessup, MD)
- …+ Experience with FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash, Perl, Python, ... for both are listed below:** **Basic Qualifications Principal Digital Verification Engineer :** + Bachelor's degree in a... FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting… more
- BAE Systems (Westminster, CO)
- …development environment to provide continuously evolving capabilities in space payloads. As an FPGA Verification engineer , you will work with a team ... including Xilinx Vivado/Vitis and Mentor Modelsim/Questasim. + Experience with OVM/ UVM Verification methodologies. + Ability to work...based on position level and/or job specifics. **Senior Principal FPGA Verification Engineer - $15K… more
- BAE Systems (Cedar Rapids, IA)
- …incentives may be available based on position level and/or job specifics. **Senior Engineer - ASIC/ FPGA Verification (hybrid)** **119641BR** EEO Career Site ... navigation missions. BAE is looking for experienced senior level ASIC/ FPGA Design Verification Engineers who can plan,...SystemVerilog/ UVM , OVM, and/or VHDL + Experience with ASIC/ FPGA design and verification tools (eg Siemens… more
- BAE Systems (Nashua, NH)
- …may be available based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)** **117194BR** EEO ... your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan,...SystemVerilog/ UVM , OVM, and/or VHDL + Experience with FPGA /ASIC design and verification tools (Mentor Questa… more
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