• Senior Rtl /FPGA Design Egineer

    Medtronic (Lafayette, CO)
    …of the programmable logic elements of medical capital equipment used in surgery. Hardware interfaces such as DAC, ADC, LCD display, DSP algorithms implemented in PL ... following and other duties may be assigned. Design FPGA RTL systems and close timing for advanced medical equipment...multiple products and platforms Debug prototype FPGA designs in hardware and in simulation Collect and refine FPGA and… more
    Medtronic (08/21/25)
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  • Principal Design Engineer Manager - AI…

    Microsoft Corporation (Redmond, WA)
    Microsoft Silicon, Cloud Hardware , and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for ... to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high...paramount importance. To achieve this goal, the AI Silicon Engineering (AISiE) team is instrumental in defining and delivering… more
    Microsoft Corporation (09/26/25)
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  • Technical Lead Manager , ASIC Design,…

    Google (Sunnyvale, CA)
    Technical Lead Manager , ASIC Design, Machine Learning + _link_ Copy link + _email_ Email a friend _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Advanced** ... a friend **Minimum qualifications:** + Bachelor's degree in Electrical Engineering , Computer Engineering , Computer Science, or a...role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive… more
    Google (09/29/25)
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  • Principal Silicon IP Program Manager

    Microsoft Corporation (Raleigh, NC)
    Microsoft Silicon, Cloud Hardware , and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for ... to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high...To achieve this goal, the Compute Silicon Manufacturing and Engineering (CSME) team is instrumental in defining and delivering… more
    Microsoft Corporation (09/27/25)
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  • Front End Lead

    Cadence Design Systems, Inc. (Austin, TX)
    …of technology. Cadence Solutions (North America) team is looking for an experienced Manager to lead Front End Design projects. This is a challenging and rewarding ... be responsible for: Technical Leadership: Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design &… more
    Cadence Design Systems, Inc. (09/24/25)
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  • ASIC/FPGA Design Engineer (SMES)

    L3Harris (Camden, NJ)
    …sign-on payment in the amount of $ 15,000 . Job Description: Reporting to the Manager , Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) ... other Friday off Are you ready to take your engineering career to the next level and be a...system requirements and developing detailed architecture + Execute design ( RTL AND/OR HLS (C++ to RTL )) and… more
    L3Harris (07/23/25)
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  • Technical Program Manager , ASIC

    Amazon (Austin, TX)
    …connectivity. The Project Kuiper team is looking for a Technical Program Manager with experience in complex ASIC/SOC development of managing various phases of ... Reliability, Qual, and NPI. The role will interface with cross-functional engineering and program/product management teams to develop ASIC/SOCs solutions that will… more
    Amazon (09/21/25)
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  • Physical Design Manager

    Cadence Design Systems, Inc. (Austin, TX)
    …an impact on the world of technology. We are looking for an experienced Manager to lead Physical Design projects. You will be responsible for identifying, defining, ... physical design flow. In this role you will drive RTL to GDS flow for microprocessor design, Engage with...high speed interconnect Qualifications + Master's degree in Electrical Engineering , Computer Engineering , or a related field… more
    Cadence Design Systems, Inc. (09/24/25)
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  • Senior Digital IC Design Engineer

    Medtronic (Tempe, AZ)
    …Responsibilities may include the following and other duties may be assigned. + RTL design from taking product specification to defining architecture, and block level ... test development through working closely with test teams. + Interact and influence product engineering , test engineering , research and FW teams as part of the… more
    Medtronic (09/30/25)
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  • ASIC Design Technical Leader - Design & Timing…

    Cisco (San Jose, CA)
    …+ Location:San Jose, California, US + Area of InterestEngineer - Hardware + Compensation Range168800 USD - 241200 USD + Job TypeProfessional ... timing modes. + Option to also do block level RTL design or block or top-level IP integration. +...**Minimum Qualifications:** + Bachelor's Degree in Electrical or Computer Engineering with 8+ years of ASIC or related experience… more
    Cisco (09/24/25)
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