• Quantum Device Design Engineer, Quantum AI

    Google (Goleta, CA)
    …delivering unparalleled performance, efficiency, and integration. As a Quantum Integrated Circuit Designer , you will support the physical design of quantum ... Quantum Device Design Engineer, Quantum AI + _link_ Copy link...Simulation tools (eg Sonnet, HFSS, Comsol). + Experience with IC fabrication techniques and processes. + Experience with Superconducting… more
    Google (10/01/25)
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  • 3D Heterogeneous Integration Design

    Global Foundries (Malta, NY)
    …(geometry rules, electrical rules, etc.) that must be followed for an integrated circuit ( IC ) design to be manufacturable. + Advanced packaging liaison to the DM ... is a leading full-service semiconductor foundry providing a unique combination of design , development, and fabrication services to some of the world's most inspired… more
    Global Foundries (07/23/25)
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  • Senior CAD Engineer, Custom Circuit Designers

    NVIDIA (Santa Clara, CA)
    …various netlisters + Install, configure and support foundry PDKs + Maintain the custom design environment used by custom schematic and mask designers + Write ... with an in-depth understanding of circuits, layouts and VLSI design . We are looking for someone who loves to...responsible for supporting and maintain CAD tools used by IC designers including Virtuoso, IC -Manage, HSPICE, ADE,… more
    NVIDIA (09/03/25)
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  • Senior Staff Semiconductor RF Test Engineer

    Northrop Grumman (Linthicum Heights, MD)
    …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. The candidate ... (ATL) located outside of Baltimore, Maryland - where we design , manufacture, and test semiconductor products for internal and...architect role in the development and execution of mixed-signal/RF IC device test solutions for products in various fab… more
    Northrop Grumman (07/08/25)
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  • Co-Op

    Skyworks (Austin, TX)
    …in Foundry PDK (Spice model, LVS, DRC, PEX, etc), CAD tools (Cadence Virtuoso) and IC design flow. The typical pay range for an Engineering intern across the ... will assist in developing the tape-out flow to enasure MASK accuracy, optimizing the system for better execution and...a technology featured based tape-out process that ensures process MASK accuracy. + Consolidate and create a DRC waiver… more
    Skyworks (09/11/25)
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  • Photonics Integration Engineer

    NY CREATES (Albany, NY)
    …our offerings. Job responsibilities include, but are not limited to: + Handling 3rd party design IP. + Design rule checking and waiver reviews. + Collection and ... with other integration team members. + Coordinating with vendors such as the mask house, dicing/packaging, and any outsourced processes + Integration support for the… more
    NY CREATES (07/19/25)
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