• Integrated Circuit ( IC ) Layout

    MIT Lincoln Laboratory (Lexington, MA)
    …development, the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout , material growth and ... and laying out devices, test structures, systems, and full mask reticles based on input from device and process...in Perl, TCL, or Python o Experience with RF layout design At MIT Lincoln Laboratory, our… more
    MIT Lincoln Laboratory (05/29/25)
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  • Quantum Device Design Engineer, Quantum AI

    Google (Goleta, CA)
    …Element Simulation tools (eg Sonnet, HFSS, Comsol). + Experience with IC fabrication techniques and processes. + Experience with Superconducting circuit ... Quantum Integrated Circuit Designer, you will support the physical design of quantum processors and associated analog, DC, and...an iterative process of working with custom programmatic CAD layout tools, graphical layout tools such as… more
    Google (08/08/25)
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  • 3D Heterogeneous Integration Design

    Global Foundries (Malta, NY)
    …(geometry rules, electrical rules, etc.) that must be followed for an integrated circuit ( IC ) design to be manufacturable. + Advanced packaging liaison to the DM ... design rules , library device ( TSV) layouts, layout vs schematic( LVS) requirements , device model terminals....vehicle content specifications and the associated tapeout process (including mask reviews ). + Develop expertise in drafting test… more
    Global Foundries (07/23/25)
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  • Senior CAD Engineer, Custom Circuit Designers

    NVIDIA (Santa Clara, CA)
    …various netlisters + Install, configure and support foundry PDKs + Maintain the custom design environment used by custom schematic and mask designers + Write ... responsible for supporting and maintain CAD tools used by IC designers including Virtuoso, IC -Manage, HSPICE, ADE,...+ A basic understanding of mosfet device behavior, CMOS layout , and VLSI design + Excellent programming… more
    NVIDIA (06/05/25)
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  • Senior Staff Semiconductor RF Test Engineer

    Northrop Grumman (Linthicum Heights, MD)
    …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. The candidate ... architect role in the development and execution of mixed-signal/RF IC device test solutions for products in various fab...hardware skills including probe card and package part fixture/DIB design & coordinating layout & assembly +… more
    Northrop Grumman (07/08/25)
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  • Photonics Integration Engineer

    NY CREATES (Albany, NY)
    …of photonic devices, specifically silicon or III-V photonics + Familiarity with IC layout and verification tools (KLayout, Cadence, Mentor Graphics, Synopsys) ... but are not limited to: + Handling 3rd party design IP. + Design rule checking and...team members. + Coordinating with vendors such as the mask house, dicing/packaging, and any outsourced processes + Integration… more
    NY CREATES (07/19/25)
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