• Senior Mask Design Engineer

    NVIDIA (Santa Clara, CA)
    …to the world. This is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer ? If yes, We would love to hear ... from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing and dynamic group of diverse individuals… more
    NVIDIA (11/13/25)
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  • Senior Mask Design Engineer

    NVIDIA (Santa Clara, CA)
    …to the world. This is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer ? If yes, We would love to hear ... from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing and dynamic group of diverse individuals… more
    NVIDIA (08/28/25)
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  • Senior Mask Design Engineer

    NVIDIA (Santa Clara, CA)
    …creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a ... a BSEE or equivalent experience. + Minimum of 8+ years industry experience in Mask and Layout Design . + Working independently on creating layout with… more
    NVIDIA (10/15/25)
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  • Principal Layout Engineer , DPG

    Micron Technology, Inc. (Boise, ID)
    …development, sharing knowledge, and innovating as one team. **Role Summary:** As a Layout Engineer in DPG, you will translate schematics into manufacturable ... productivity gains. Integrate automated layout solutions to shape the future of layout design . + On‑Time Delivery: Coordinate with global partners to meet… more
    Micron Technology, Inc. (10/08/25)
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  • Senior Analog Layout Engineer

    Capgemini (Minneapolis, MN)
    …find the fastest way to complete layout * Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent ... **About the job you're considering** * 10 years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3 years of recent… more
    Capgemini (10/23/25)
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  • Layout Designer

    Texas Instruments (Phoenix, AZ)
    …Associate's degree in Engineering or related field of study or program certificate in Advanced IC Mask Layout Design + Minimum 3.0 out of 4.0 cumulative GPA ... and Digital design teams and the global layout design community + Understanding manufacturing rules...or work authorization for this position.** **Why TI?** + Engineer your future. We empower our employees to truly… more
    Texas Instruments (11/08/25)
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  • Analog Mixed Signal Integrated Circuit…

    Google (Mountain View, CA)
    …internally built integrated circuits. + Oversee physical design and guide mask designers to create high quality layout . Information collected and processed ... Analog Mixed Signal Integrated Circuit Design Engineer _corporate_fare_ Google _place_ Mountain...IC design . + Experience in transistor-level schematic design , layout , simulation, and verification. + Experience… more
    Google (11/13/25)
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  • Senior SRAM Engineer , Circuit…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior SRAM Engineer ! The Full Custom Macro team at NVIDIA designs specialized RAM implementations for NVIDIAs wide array of processing ... circuits that help power these chips. What you'll be doing: + Design best-in-class SRAM circuits using state-of-the-art technology processes + Optimize circuits for… more
    NVIDIA (10/03/25)
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  • 3D Heterogeneous Integration Design

    Global Foundries (Malta, NY)
    …www.gf.com . Summary of Role: GlobalFoundries Fab8 is seeking a motivated R&D design enablement engineer to become part of our state-of-the-art 300mm fabrication ... design rules , library device ( TSV) layouts, layout vs schematic( LVS) requirements , device model terminals....vehicle content specifications and the associated tapeout process (including mask reviews ). + Develop expertise in drafting test… more
    Global Foundries (11/09/25)
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  • Quantum Hardware Design Engineer

    IBM (Yorktown Heights, NY)
    …and related testsites * Connectivity/schematic capture for quantum hardware releases * Detailed mask layout and chip finishing for quantum hardware releases * EM ... all levels of design tapeouts using custom design tools, including block-level and chip-level layout ....custom design tools, including block-level and chip-level layout . Applicants are expected to have experience with relevant… more
    IBM (11/14/25)
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