- Northrop Grumman (Jessup, MD)
- …Principal level. Qualifications for both are listed below:** **Basic Qualifications for Principal Digital ASIC Circuit Design Engineer Level:** + ... constraints and timing closure. Automated place and route and physical verification knowledge is a plus. Must have strong...(Synopsys Design Constraints) **Basic Qualifications for Sr. Principal Digital ASIC Circuit Design … more
- SpaceX (Redmond, WA)
- Principal ASIC Design Engineer (Silicon Engineering) Redmond, WA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. PRINCIPAL ASIC DESIGN ENGINEER (SILICON...Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check) +… more
- Palo Alto Networks (Santa Clara, CA)
- …military experience required - MSEE preferred + Minimum 5 years experience in ASIC design verification + Demonstrated success in taking multiple ASIC ... relationships, and the kind of precision that drives great outcomes. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that the… more
- Palo Alto Networks (Santa Clara, CA)
- …precision that drives great outcomes. **Your Career** As a Systems Administrator in the ASIC / FPGA team you will interface with engineering teams regularly to help ... and maintain a world-class semiconductor development environment. You will work with multiple ASIC and FPGA engineering teams as well as IT and Infosec to build… more
- Northrop Grumman (Linthicum Heights, MD)
- …or propose changes to fix them + Work closely with design , verification, design -for-test and physical design teams to optimize the timing and improve ... + 4 years of experience in the full product life cycle of ASIC Design **Preferred Qualifications:** + Master's Degree in Electrical or Computer Engineering +… more
- Broadcom (Irvine, CA)
- …you apply.** **Job Description:** Broadcom is seeking a highly experienced and accomplished Principal ASIC Chip Lead to lead the development of cutting-edge ... role requires a deep, end-to-end understanding of the entire ASIC architecture, design , and verification flow-from initial...plan, coverage plan, and coverage closure + Work with physical design team on design … more
- Renesas (Duluth, GA)
- …writing device-level or sub-system specifications. + **Fluent in Verilog RTL coding and ASIC design methodology** + Expertise in digital design ... Principal Digital Design Engineer Job Description +...ATE support (a plus) + Experience in DFT or physical design (a plus) Company Description Renesas is… more
- SpaceX (Hawthorne, CA)
- Principal RFIC Design Engineer Hawthorne, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally ... possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL RFIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology… more
- Silvus Technologies (Los Angeles, CA)
- …presentation skills. + Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL REQUIREMENTS + Office environment. ... fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer- Signal Processing_** who will report to the _Director of FPGA… more
- SanDisk (Milpitas, CA)
- …requirements to various functions of Memory teams to meet systems specs. + Define ASIC requirements for upcoming new NAND Flash based chips and design systems ... years of working experience in NAND flash based systems or relevant systems design PREFERRED: + Knowledge of programming in high-level languages (eg C, C++, Python)… more