- Monster (Alamogordo, NM)
- …TMB Louisiana: LRT (R) or (F) by LSRTBE New Mexico: RRT by MIRTP NMED Arkansas: RTL by Arkansas Department of Health BLS required Work Schedule: 5 Days - 8 Hours ... Work Type: Full Time EEO is the law - click below for more information: https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf We endeavor to make this site accessible to any and all users. If you would like to contact us… more
- Silvus Technologies (Irvine, CA)
- …fulfilling career._ THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for Irvine ... aimed at addressing challenging real-world communication needs. The Principal FPGA / RTL Design Engineer position will be based at Silvus' Irvine CA engineering… more
- Amazon (Boise, ID)
- …Fire TV and Amazon Echo. What will you help us create? The Role: As an RTL Design Engineer, you will be part of an advanced architecture team that is exploring new ... will be responsible for defining the micro-architecture and implementing the corresponding RTL for advanced functional blocks. You will participate in the design… more
- Broadcom (Fort Collins, CO)
- …most advanced wireless solutions, as some examples. The _Interface and Analog IP RTL Design Manager_ position is part of a cross functional design team developing ... will lead the team that architects and writes the RTL code that creates the digital function and integrates...+ Lead & manage a team of high performance RTL design engineers in the development of complex … more
- Broadcom (San Jose, CA)
- …before you apply.** **Job Description:** **Broadcom is looking for a senior level RTL synthesis engineer. In this highly visible role, you will be contributing to ... Power.** + **Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.** + **Deep...and design flow.** + **Run Formal Verification checks between RTL and Gate level netlist and debug the aborts,… more
- Cisco (San Jose, CA)
- Senior DFx/ RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT… more
- Broadcom (San Jose, CA)
- …apply.** **Job Description:** **Broadcom is looking for a high-speed DSP SerDes RTL designer. Qualifications include:** + **MS or PhD in Electrical Engineering or ... Engineering with 10+ years of experience in high speed ADC based SerDes RTL design.** + **Proficient with Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes… more
- Arrow Electronics (Santa Clara, CA)
- **Position:** RTL Design Engineer (eInfochips) **Job Description:** **Role: RTL Design Engineer** **Location: San Jose CA (Remote)** **Experience: 10+ Years** ... **What candidate will Be Doing:** + Strong expertise on Arteris Design Toolset (Like Mansour Amirfathi) + At-least 5+ years of experience in Verilog Design + AMBA AXI bus along-with ARM or C based processor + Ensure customer satisfaction. + Reporting to… more
- St John's Community Services (Martin, TN)
- TEAM LEAD RESIDENTIAL ( RTL )-Martin, TN Job Details Job Location Martin - Martin, TN Position Type Full Time Education Level High School Salary Range $18.62 Hourly ... Job Shift Multiple Job Category Nonprofit - Social Services Description Mission: To advance inclusive communities where every person, regardless of circumstances, has the right and opportunity to live their best life. Core Values: We believe each person… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design, debug and functional verification + Strong background in DSP and ... algorithms is a plus. + Familiar with the PMA/PMD/PCS layers of the Ethernet protocol is a plus. + Understanding of digital architecture trade-offs for power, performance, and area + Understanding of proper handling of multiple asynchronous clock domains and… more
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