- NVIDIA (Santa Clara, CA)
- …are groundbreaking in AI and computing. What you'll be doing: As a Reliability Methodology Engineer at NVIDIA, you will be responsible for ensuring our products ... + Collaborate with design, product, and test engineering teams to apply DFT methodologies to improve reliability screening specific to HTOL (Component level Hight… more
- Amazon (Cupertino, CA)
- …integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, ... physical design work. Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies. Be able to independently… more
- Cisco (San Jose, CA)
- Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... & IP integration; familiarity with functional verification **Preferred Qualification:** + DFT CAD development - Test Architecture, Methodology and Infrastructure… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you ... BIST, etc. + Knowledge of clocking and clock controls in DFT modes. + Experience in methodology or flow development. NVIDIA is widely considered to be one… more
- NVIDIA (Santa Clara, CA)
- …and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you ... You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL synthesis and gate level...power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure functional and timing… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS...GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS...or Network processor implementation or SOCs. + Understanding of DFT logic and experience with DFT timing… more
- Renesas (Duluth, GA)
- Senior Staff Digital Engineer Job Description + **Education:** Bachelor or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or ... sub-system specifications. + Fluent in Verilog RTL coding and ASIC design methodology + Expertise in digital design implementation, including logical synthesis and … more
- NVIDIA (Santa Clara, CA)
- …position within a top-tier organization? In the role of Silicon Product Development Engineer at NVIDIA, you will be instrumental in launching our brand new Data ... ASIC Mixed Signal design, characterization, and qualification of BIST and SCAN DFT methodologies. + Knowledgeable in advanced Silicon Process technology such as… more
- Amazon (Redmond, WA)
- …un-served and under-served communities around the world. Come work at Amazon! As Senior RF ATE Engineer , you will engage with an experienced cross-disciplinary ... collaborative peer environment. You'll be responsible for RFIC high-volume production test methodology of mm-wave RFICs for Project Kuiper custom silicon. You'll be… more
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