- Qualcomm (San Diego, CA)
- …and graphics content of the most advanced mobile devices on the market. Graphics formal verification positions involve the developing high-quality formal ... high quality. Must be proficient in debugging, deep bug hunting, formal tools, formal verification methodologies and processes. Candidate should be… more
- Google (Seattle, WA)
- …community at large, helping to influence the development of sustainable formal verification tooling. + Work with other senior engineers at Google, across ... 8 years of experience working in the area of formal verification . + 5 years of experience...on and is growing every day. As a software engineer , you will work on a specific project critical… more
- Capgemini (Seattle, WA)
- **Job Role:** **SOC Design Verification Engineer ** **Job location: Seattle WA** **Job Description:** We are looking for SOC Design Verification Engineer ... + Experience in one or more of the following areas along with functional verification -SV Assertions, Formal , Emulation. + Experience in EDA tools and scripting… more
- Jet Propulsion Laboratory (Pasadena, CA)
- …Digital Electronics Group** . We are seeking a **Field Programmable Gate Array (FPGA) Verification Engineer IV** , responsible for the verification of the ... methodology aligned to the test plan. + Apply formal methods to supplement simulation-based verification . +...+ Apply formal methods to supplement simulation-based verification . + Systematically analyze, track and resolve design bugs… more
- Amazon (Sunnyvale, CA)
- …Neural Edge that is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of ... performance industry standard buses like AMBA AXI4 - Experience with formal verification - Experience with post-silicon validation - Experience with embedded… more
- NVIDIA (Santa Clara, CA)
- The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification . The NVIDIA Clocks ... in industry-standard verification flows like SV constraint random verification , UVM, Formal Verification , Coverage metrics, profiling tools, X prop, etc.… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... silicon correlation. + Own the unit and sub-system level verification of various IPs, create functional test plans, and...as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains. + Proficiency in scripting language, such… more
- Google (Mountain View, CA)
- …Computer Engineering, or Computer Science. + Experience in different verification techniques and methodologies including formal , Gate-Level Simulation, ... field, or equivalent practical experience. + 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. + Experience… more
- Huntington Ingalls Industries (Roanoke, VA)
- …Range: - $135,000.00 Security Clearance: Ability to Obtain Level of Experience: Senior This opportunity resides with Warfare Systems (WS), a business group within ... https://vimeo.com/732533072 Job Description Do you enjoy challenging digital design verification problems? HII Mission Technologies is seeking out-of-the-box thinkers… more
- Qualcomm (Boxborough, MA)
- …position available now. We are looking for a self-driven person with CPU/GPU/DSP verification knowledge using random test generation or formal methodologies and ... Group > GPU ASICS Engineering **General Summary:** Bring your hardware verification skills to a fast-moving, high-value team within Qualcomm. Qualcomm's GPU… more
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