- SpaceX (Irvine, CA)
- …into physical design flow + Work with systems and architecture, SOC integration, verification, DFT, mixed signal, IP owners, synthesis, and place/route teams to ... Debug and drive fixing of constraint correlation issues between top and block level + Develop clock...deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA/Timing Engineer/ Level I: $120,000.00 - $145,000.00/per… more
- SpaceX (Irvine, CA)
- …STA Signoff. + Experience with power intent and upf development for block and soc top . + Familiar with formal verification and implementing functional ecos. + ... Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer (Silicon... and timing closure + Deep understanding of ASIC design flow, top -down and bottom-up design… more
- Capgemini (MN)
- …and improving UVM based verification methodology * Ability to context switch from unit level verification to top level verification * Knowledge of ARM ... **Job description:** We are looking for a Senior Hardware SoC Model Engineer with expertise in Renode. The ideal...virtualized embedded hardware systems in a simulation environment. * Design , develop, and execute unit tests to validate model… more
- Datavant (Denver, CO)
- …Looking For** Become a vital defender of our digital landscape as a SOC /SIRT engineer. You'll monitor and analyze security alerts, swiftly respond to incidents, and ... collaborate with top IT and security teams to fortify our defenses....coordination and communication across technical teams and stakeholders. + Design , mature, and implement advanced playbooks for triage, investigation,… more
- The Boeing Company (Tukwila, WA)
- …(Virtuoso suite and Spectre simulator products) + Experience working on large-scale SoC design teams. + Experience developing Mixed-Signal circuits in ... actively hiring an **Analog Mixed Signal Integrated Circuit (IC) Design Engineer (Mid- Level or Lead),** who has...Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include… more
- Cisco (San Jose, CA)
- …and supporting our prototyping methodology * Option to engage in block- level RTL design or block or top - level IP integration * Collaborate with Software, ... Technical Leader with primary focus on FPGA Prototyping * Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds,… more
- Amazon (Sunnyvale, CA)
- …buses like AMBA AXI4 - Experience in integrating third party IP blocks, building top level modules, defining clock domains and power domains - Large breadth ... in consumer devices. They should be familiar with modern SoC architectures, various interconnect topologies such as AMBA AXI,...with ARM and various DSP ISA - Experience debugging system- level issues - Experience in entire design … more
- Amazon (Austin, TX)
- …the right trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing ... Engineering or related technical field - 5+ years of experience in RTL design for SOC - 5+ years of experience VLSI engineering - 5+ years of experience… more
- Meta (San Diego, CA)
- …verification and UVM methodology. 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 10. ... the testing infrastructure to validate new core IP or SoC implementations. You will work closely with researchers, architects...track detailed test plans for the different modules and top levels. 3. Drive Design Verification to… more
- Amazon (Austin, TX)
- …implementing robust integration methodologies - Have deep expertise in high-performance SOC design , including clock/reset architecture, timing closure, and CDC ... chips - Drive technical decisions across multiple disciplines (RTL, timing, DFT, physical design ) - Ensure on-time delivery of complex SOC integration milestones… more