- SpaceX (Sunnyvale, CA)
- Sr . SOC/ ASIC Physical Design Methodology/ CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where ... of enabling human life on Mars. SR . SOC/ ASIC PHYSICAL DESIGN METHODOLOGY/ CAD ENGINEER ...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- Honeywell (Phoenix, AZ)
- …IC Design platform needs spanning IC Design cell development, macrocell development, ASIC design systems, physical verification and mask- CAD flows. **WE VALUE** ... You will report directly to the Senior Engineering Manager and you'll work at our...IC Design engineers to craft and maintain optimized EDA CAD flows for a highly heterogeneous set of IC… more
- Amazon (Austin, TX)
- …deliver results that help our customers change the world. We are seeking an experienced Senior Substrate CAD layout Engineer for the next generation of our ... and want to reach beyond what is possible today. As a Substrate/PCB layout engineer , you will participate in the definition and implementation of substrate and PCB… more
- NVIDIA (Santa Clara, CA)
- We are looking for a motivated Senior Synthesis Flow CAD Engineer to join our growing team! Are you a computer engineer with a passion for automation of ... employing advanced silicon processes. We're responsible for NVIDIA's front-end ASIC implementation flows-including RTL synthesis, equivalence checking, and early… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... (RTL2GDS) for ML Accelerator chips in advanced nodes Drive Optimizations in CAD flows/methodologies for PPA and TAT improvements Work with EDA tool vendors… more
- NVIDIA (Santa Clara, CA)
- …lasting impact on the world! We are currently looking for a Senior Methodology Engineer to develop and support our CAD tooling in our Circuit Solutions Group ... equivalent experience + 3+ years of experience in VLSI CAD flows and methodology + Timing closure and STA...out from the crowd: + Previous work in VLSI, ASIC , or EDA is a definite plus + Experience… more
- Amazon (Austin, TX)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and ... MS + 6yrs in EE/CS - 6+ years in ASIC Physical Design from - RTL-to-GDSII in either 7nm,...Tcl, Perl or Python Preferred Qualifications - Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others)… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human inventiveness and intelligence. NVIDIA's ASIC -PD Methodology organization is driving the next generation of AI-assisted timing ... closure across multi-billion transistor chips. We are seeking an Applied AI Engineer to lead end-to-end solution development - spanning data generation, model… more
- NVIDIA (Santa Clara, CA)
- …in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the ... Layout team, you will collaborate to implement high speed/density ASIC packages. + Perform substrate breakout patterns for ...size, cost, and system performance. + Develop symbols and CAD library databases using Cadence APD design tools +… more