- SpaceX (Irvine, CA)
- Sr . ASIC Design Engineer (Silicon Engineering)...clean design + Participate in all phases of ASIC and/or FPGA design flow (eg ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER (SILICON...and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC Design Engineer/ Senior : $160,000.00 -… more
- Arrow Electronics (San Jose, CA)
- **Position:** Senior ASIC Design Engineer (eInfochips Inc) **Job Description:** **What candidate will Be Doing:** + Map multi-million gate SoC designs ... or a related discipline. + A comprehensive understanding of ** FPGA design ** , with proven expertise in...design ** , with proven expertise in partitioning multi-million gate designs across multiple FPGAs. + Proficiency in **synthesis,… more
- The Boeing Company (Tukwila, WA)
- …Weapons Systems has an exciting opportunity for an ** ASIC and/or FPGA Design and Verification Engineer** (Experienced, Lead or Senior ) to join us as part ... across the company and around the world and support ASIC / FPGA design and verification for...HDL coding, and physical design realization (through gate -level netlists for ASIC designs) + Integrate… more
- The Boeing Company (Fairfax, VA)
- …Systems has an exciting opportunity for multiple ** ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal)** to join us as part ... across the company and around the world and support ASIC / FPGA design and verification for...HDL coding, and physical design realization (through gate -level netlists for ASIC designs) + Integrate… more
- Palo Alto Networks (Santa Clara, CA)
- …expertise on the entire ASIC design flow-architecture, logic design , RTL coding, verification, FPGA validation, synthesis, DFT, timing closure and ... with precision. **Your Career** We are looking for a Senior Director of ASIC Engineering to manage...10+ year industrial experience + Minimum of 10 years ASIC design /verification and 5 years of … more
- University of Southern California (Arlington, VA)
- …Research Engineer - Digital DesignApply (https://usc.wd5.myworkdayjobs.com/ExternalUSCCareers/job/Arlington-VA/ ASIC - FPGA -Research-Engineer Digital- Design ... - Digital Design , to perform front-end digital design of advanced ASIC or FPGA...solutions to novel research problems + Work closely with senior researchers and contribute to team efforts to transform… more
- RTX Corporation (Cedar Rapids, IA)
- …integration + Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow + Contribute to engineering estimates ... for a security clearance **Security Clearance:** DoD Clearance: Secret ** Senior Electrical Engineer** **- ASIC / FPGA ...Will Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL,… more
- Amazon (Redmond, WA)
- …(SOC / ASIC leads) to create project execution plans for ASIC / FPGA development considering all criteria to design products the meet the power/performance ... other organizations operating in places without reliable connectivity. The Senior Manager for ASIC Technical Program Manager...functional programs with aggressive schedules - 5+ years of ASIC /SOC design and/or management experience - 5+… more
- Lockheed Martin (Liverpool, NY)
- …to complex problems which require the regular use of ingenuity and creativity applied to FPGA design and/or board design \. * Working knowledge of digital ... they fit together\. **A level 3 employee is typically senior \-career and has 3 to 5\+ years of professional...relevant work experience * Prior technical leadership experience * FPGA architecture and design , with applied knowledge… more
- Lockheed Martin (Denver, CO)
- …will accomplish in this role:** * Support other aspects of ASIC and FPGA development such as architecture, design , analysis, and test\. * Support technical ... the design \. * Support other aspects of ASIC and FPGA development such as architecture,... \(MBSD\)\. * Metrics collection, analysis, and reporting to senior leadership\. **Security Clearance Statement:** This position requires a… more