• Senior SOC Pre-Silicon Verification

    Micron Technology, Inc. (Richardson, TX)
    …that are transforming how the world uses information to enrich life. As an HBM SOC Pre-Silicon Verification Engineer , you will be responsible for the design ... Logic chip can use a full ASIC flow. Lastly, verification and testing (validation) of HBM is the most...exciting. **What's Encouraged Daily:** + Develop test plans at IP/ Subsystem / SOC Level. + Review architectural specifications to… more
    Micron Technology, Inc. (04/19/25)
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  • Low Power ASIC Engineer (Next-Gen,…

    Qualcomm (San Diego, CA)
    …designs. + Strong knowledge in the entire low power, high performance ASIC/ SoC design flows (micro-architecture, RTL design, verification , synthesis, timing/STA, ... This is a great opportunity to join a fast-paced SoC team responsible for development of next Generation, high...development of next Generation, high performance, low power Memory Subsystem RTL Design, flows and methodology for high performance… more
    Qualcomm (02/15/25)
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  • SoC RTL Design Engineer

    Google (Sunnyvale, CA)
    …Experience developing common library RTL modules and working on PCIe verification and bringup. + Understanding of digital design fundamentals, including synchronous ... this role, you will join a team working on SoC -level RTL design for our data center accelerators. You...(RTL) IP with the focus on management and control subsystem , also participate in developing infrastructure and methodology that… more
    Google (04/23/25)
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  • ASIC Engineer , Memory Management Design…

    Meta (Sunnyvale, CA)
    …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... silicon success. **Required Skills:** ASIC Engineer , Memory Management Design Verification Responsibilities: 1. Define and implement IP/ SoC verification more
    Meta (03/04/25)
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  • ASIC, Design Verification Engineer

    Meta (Austin, TX)
    …IP/ SoC verification plans, build verifications test benches to block IP/ subsystem / SoC level verification and develop functional tests based Debug, ... "Apply to Job" online on this web page. **Required Skills:** ASIC, Design Verification Engineer Responsibilities: 1. Develop functional tests based on … more
    Meta (03/18/25)
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  • Design Verification Engineer

    Qualcomm (San Diego, CA)
    …, & SoC integration teams to complete the successful PHY level verification , integration into subsystem and SoC , and post-silicon validation. + ... Engineering Group > ASICS Engineering **General Summary:** Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs (PCIe, USB,… more
    Qualcomm (04/19/25)
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  • ASIC Engineer , Formal Verification

    Meta (Salt Lake City, UT)
    …to build IP and System On Chip ( SoC ) for data center applications. As a Formal Verification Engineer , you will be part of a team working with the best in the ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization....with targeted Formal Verification Techniques at IP, Subsystem and SoC level 5. Build reusable/scalable… more
    Meta (03/22/25)
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  • Sr. ASIC Design Verification

    Qualcomm (Austin, TX)
    …such as UVM or OVM or similar methodologies. + Experienced in developing IP or Subsystem level or SoC level test planning + Understanding of PCIe and/or CXL ... connected future for all. The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The… more
    Qualcomm (04/14/25)
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  • CPU Verification Engineer (Multiple…

    Qualcomm (Santa Clara, CA)
    …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer , you will work with Chip Architects to validate the ... concepts of CPU and SOC level micro-architectures. You will work on a selected...work on a selected part of the CPU Design Verification to ensure that it functions to the standards… more
    Qualcomm (04/04/25)
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  • Senior FPGA Design Engineer

    Jet Propulsion Laboratory (Pasadena, CA)
    …Systems Group** . We are seeking a **Field Programmable Gate Array (FPGA) Engineer IV** , responsible for the design and implementation of digital subsystems for ... mission critical events and interface compatibility testing; monitor operational subsystem performance; assist Radar Operations with performance issues and… more
    Jet Propulsion Laboratory (02/05/25)
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