• ASIC Verification - Team Lead

    Microsoft Corporation (Santa Clara, CA)
    … UVM /SystemVerilog-based testbenches for block-level, cluster-level, fullchip and emulation verification + Comfortable and experienced with AI based tools ... to accelerate productivity. + Experience with coverage- driven verification , functional coverage, and code coverage analysis. + Execute simulations using… more
    Microsoft Corporation (01/09/26)
    - Related Jobs

  • ASIC Design Verification Engineer,…

    Google (Sunnyvale, CA)
    …complex digital designs, with a specific focus on TPU architecture and its integration within AI /ML- driven systems. In this role, you will use your design and ... this role, you'll work to shape the future of AI /ML hardware acceleration. You will have an opportunity to... verification scenarios. + Create and enhance constrained-random verification environments using SystemVerilog and UVM , or… more
    Google (12/17/25)
    - Related Jobs

  • ASIC Design Verification Engineer I (Full…

    Cisco (San Francisco, CA)
    …and timing closure. **Preferred Qualifications** ** ** + Experience with ASIC verification methodologies (eg, UVM , SystemVerilog) + Understanding of physical ... developing and bringing new products to market across Cisco's product line. Open-minded, driven , diverse and deeply creative people at Cisco craft the hardware that… more
    Cisco (12/16/25)
    - Related Jobs

  • Lead Electronics & Semiconductor Engineer

    Capgemini (Santa Clara, CA)
    …, **define risk-mitigated strategies** , and **recommend innovative approaches** (including AI - driven enhancements) for SoC verification and design. ... + **Architect and Implement Solutions** Design and deploy **end-to-end** **SoC** ** verification environments** leveraging UVM , UPF, and advanced methodologies.… more
    Capgemini (12/30/25)
    - Related Jobs

  • Staff Logic Design Engineer

    Teledyne (Milpitas, CA)
    …+ Integrate PCIe IP cores, DMA engines, and custom protocol decoders. + ** Verification & Debug** + Build SystemVerilog/ UVM testbenches for block and system-level ... system companies to validate and debug cutting-edge technologies in data centers, AI /ML, storage, and networking. **Role Overview** We are looking for a top-notch… more
    Teledyne (11/18/25)
    - Related Jobs