• ASIC / SOC DFT

    SpaceX (Sunnyvale, CA)
    ASIC / SOC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... to make this possible, with the ultimate goal of enabling human life on Mars. ASIC / SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
    SpaceX (09/18/25)
    - Related Jobs
  • DFT Engineer

    Broadcom (San Jose, CA)
    …have a Candidate Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking ... to production. The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD ( ASIC Products Division)'s designs - … more
    Broadcom (09/05/25)
    - Related Jobs
  • Sr Principal DFT Application…

    Cadence Design Systems, Inc. (San Jose, CA)
    …world of technology. We are looking for SoC / ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and experience ... preferred. + Prior 5-15 years of professional experience in SoC / ASIC Digital Design with focus on Design... Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT more
    Cadence Design Systems, Inc. (10/30/25)
    - Related Jobs
  • Senior ASIC Design Engineer - DFX

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products....verification of DFT IPs for our next-generation SoC products. You'll help drive innovation across the full… more
    NVIDIA (10/25/25)
    - Related Jobs
  • ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of ... like CHI/CXL/PCI-E is a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT , timing analysis, floor planning,… more
    NVIDIA (10/25/25)
    - Related Jobs
  • ASIC Design Engineer , Cloud-Scale…

    Amazon (Cupertino, CA)
    …trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/ DFT signal routing - As a key ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies...or equivalent - 3+ years in RTL design for SOC - 3+ years of VLSI engineering - 3+… more
    Amazon (10/31/25)
    - Related Jobs
  • ASIC Engineer , Implementation

    Meta (Sunnyvale, CA)
    …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... work w/ designers to create waivers. 6. Perform RTL DFT analysis and improve DFT coverage for...for RTL-synthesis and PrimeTime-STA for blocks and top-level including SOC . 11. Analyze inter-block timing and create IO budgets… more
    Meta (09/20/25)
    - Related Jobs
  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is ... high-quality clocking and reset logic to various units in SOC and GPU ASIC . The complexity of...implementing Test plans for pre-silicon platforms. + Understanding of DFT /IST is optional. We have some of the most… more
    NVIDIA (11/07/25)
    - Related Jobs
  • Senior ASIC Design Engineer - Clocks…

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams.... teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes,… more
    NVIDIA (10/28/25)
    - Related Jobs
  • Sr. Full Chip Physical Design Engineer

    SpaceX (Sunnyvale, CA)
    …bus routing, sequential pipeline planning and top level design for testability ( DFT ) planning + Collaborate with chip architects, ASIC engineers, package ... Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring… more
    SpaceX (11/14/25)
    - Related Jobs