• ASIC Automation…

    Broadcom (Irvine, CA)
    …design background is preferred & the candidate should have a strong scripting/ automation experience using Python / Perl Must have strong communication and ... documentation skills. Must be a self-starter and a strong team player. Candidates will primarily be responsible for working on automating design flows, supporting synthesis deliverables & STA. Apart from this, the candidate is also expected to handle minimal… more
    Broadcom (04/22/25)
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  • Low Power ASIC Engineer (Next-Gen,…

    Qualcomm (San Diego, CA)
    …Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration , or related work experience. OR ... Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration , or related work experience. OR PhD… more
    Qualcomm (05/17/25)
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  • Digital ASIC Design Engineer…

    Qualcomm (San Diego, CA)
    …Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration , or related work experience. OR ... low-power digital design - Experience in creating tools and automation flows (in Python, Perl, or C) for improving...Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration , or related… more
    Qualcomm (04/19/25)
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  • ASIC Engineer , Methodology

    Meta (Sunnyvale, CA)
    …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Methodology Responsibilities: 1. Collaborate with ASIC vendor ... **Summary:** Meta is hiring Application-Specific Integrated Circuit Engineer ( ASIC ) Methodology Engineer our Infrastructure organization, where you'll play a… more
    Meta (06/25/25)
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  • ASIC Design Verification Engineer

    Qualcomm (San Diego, CA)
    …Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration , or related work experience. OR ... Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration , or related work experience. OR PhD… more
    Qualcomm (06/18/25)
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  • ASIC Design Engineer - Design…

    Cisco (San Jose, CA)
    …aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready ... ASIC Design Engineer - Design &...exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation , you excel at identifying and resolving timing issues… more
    Cisco (06/25/25)
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  • ASIC Implementation Engineer…

    Meta (Sunnyvale, CA)
    … Implementation Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. ... Gate Level Netlist for Timing, Area, Power 6. Developing Automation scripts and Methodology for all Front-end tools including...Experience with SOC CDC signoff 12. Knowledge of SOC Integration (Clocking, Reset, PLL, etc) 13. Knowledge of front-end… more
    Meta (06/25/25)
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  • ASIC Design Engineer , Cloud-Scale…

    Amazon (Cupertino, CA)
    …and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while… more
    Amazon (06/18/25)
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  • Senior ASIC Design Verification…

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... architecture, intent, and implementation of the various IPs. + Enable system level integration by working with partner teams for test development & debug and… more
    NVIDIA (06/06/25)
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  • Static Timing Analysis Engineer , FullChip/…

    Google (Mountain View, CA)
    …+ 5 years of technical experience in silicon timing closure and chip integration . + Experience with STA signoff constraint authoring for full-chip level, tapeout ... signoff requirements, checklists, and associated automation . + Experience in one or more static timing...silicon in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis.… more
    Google (06/21/25)
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