- MatX (Mountain View, CA)
- …milestones including design freeze and tapeout Work closely with the verification, DFT and physical design co-owners of the subsystem/block in question and deliver ... and related flows to take designs to high quality sign-off Experience on DFT and physical design concepts and methodologies to achieve high test coverage and… more
- OMNIVISION (Santa Clara, CA)
- …validation; Work closely with back-end team in floor-planning, timing closure and DFT ; Conduct image sensor array/analog related timing control design and STA; ... PRD/design specification and system architecture of SoC CIS products, following ASIC design flow: coding, simulation, synthesis, static timing analysis, formality… more
- Broadcom, Inc. (San Jose, CA)
- …with DV for test methodologies and verification. Providing guidelines for GLS, DFT & Verification. Hands on experience in providing guidelines for design constraints ... tape-out to foundries and solid understanding of supply chain for ASIC product development. Strong analytical thinking and problem-solving skills with excellent… more
- Meta (Sunnyvale, CA)
- … DFT EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer , DFT Responsibilities: 1. Develop and implement DFT ... **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and… more
- Qualcomm (Santa Clara, CA)
- …digital transformation to help create a smarter, connected future for all. As a DFT Engineer you will work with chip architects, chip designers, implementation ... in digital ASIC design; experience using Verilog or VHDL + Experience with ASIC test, DFT , and debug + 2+ years of practical experience with test or DFT … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...CMOS analog circuit and physical design + Knowledge of DFT /Scan/MBIST/LBIST and understanding of their impact on physical design… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We...with the Designers to create waivers 6. Perform RTL DFT Analysis and improve the DFT coverage… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you ... intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL...power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure functional and timing… more
- Cisco (San Jose, CA)
- …aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready ... ASIC Design Engineer - Design &...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more
