• ASIC Engineer , Physical

    Meta (Sunnyvale, CA)
    …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend… more
    Meta (04/22/25)
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  • Sr. SOC/ ASIC Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
    SpaceX (04/15/25)
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  • Senior ASIC Physical Design

    NVIDIA (Santa Clara, CA)
    …life's work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and ... inventiveness and intelligence. What you'll be doing: + Drive next generation physical design work to achieve best in class PPA for high-performance designs, eg… more
    NVIDIA (04/09/25)
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  • ASIC Physical Design

    Amazon (Cupertino, CA)
    …you - come build the future with us! Key job responsibilities * Perform physical design for Amazon's machine learning custom silicon solutions * Participate in ... various aspects of physical design : full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route, power integrity… more
    Amazon (04/04/25)
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  • Sr. Physical Design Engineer

    Amazon (Cupertino, CA)
    …we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze ... Basic Qualifications - BS + 8yrs or MS + 6yrs in EE/CS - 6+ years in ASIC Physical Design from - RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm - Block … more
    Amazon (03/04/25)
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  • Sr. Physical Design Methodology…

    Amazon (Cupertino, CA)
    …and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies ... in programming/scripting languages (Perl, Python, C++) - Solid understanding of ASIC physical design , and methodologies including synthesis, place and route,… more
    Amazon (03/29/25)
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  • ASIC and/or FPGA Design

    The Boeing Company (Huntington Beach, CA)
    …and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate ... & Weapons Systems has an exciting opportunity for multiple ** ASIC and/or FPGA Design and Verification Engineers...Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products… more
    The Boeing Company (04/06/25)
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  • Sr. ASIC Design Engineer

    SpaceX (Irvine, CA)
    Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING)...age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants… more
    SpaceX (04/15/25)
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  • Senior ASIC Design Engineer

    Palo Alto Networks (Santa Clara, CA)
    …meet aggressive goals for area, timing, power, and testability in close collaboration with ASIC physical design engineers + Perform synthesis + Optimize ... we all win with precision. **Your Career** As a Design engineer on the ASIC ...+ Debugging simulation, emulation, and silicon validation + Analyzing physical design reports and fixing timing and… more
    Palo Alto Networks (03/19/25)
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  • Next-Gen, High-Speed Memory Subsystem ASIC

    Qualcomm (San Diego, CA)
    …and Advanced Memory NoCs based Subsystem Design Team is looking for ASIC Design Engineers for the next generation high speed LPDDR/DDR memory subsystems.. ... into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power...in Science, Engineering, or related field. + 5+ years ASIC design , RTL coding, front-end digital … more
    Qualcomm (02/19/25)
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