• ASIC Engineer , Power

    Meta (Sunnyvale, CA)
    …technology. To apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Power Responsibilities: 1. Develop power vectors ... for estimation and optimization. 2. Low- power design of ASIC modules. 3. Run industry standard EDA power simulation tools on customized ASIC designs. 4. … more
    Meta (10/26/25)
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  • Senior ASIC Power Engineer

    Google (Sunnyvale, CA)
    Senior ASIC Power Engineer , ML Accelerators _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... + 5 years of experience in logic design, digital ASIC , or SoC design. + Experience with RTL (Register...Level) design using Verilog or SystemVerilog. + Experience with low- power design or power reduction methodologies/techniques. **Preferred… more
    Google (12/04/25)
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  • Low Power ASIC Engineer - New…

    NVIDIA (Santa Clara, CA)
    …we can make a lasting impact on the world! We are now looking for an Low Power Design/Verification ASIC Engineer - New College Grad 2026. We continue to ... a wide range of sectors. Come join NVIDIAs Low Power DV team to develop state of the art...team to develop state of the art GPUs to power AI, Automotive, GeForce, and Mobile products. What you'll… more
    NVIDIA (11/18/25)
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  • Senior ASIC Engineer - SDC

    Cisco (San Jose, CA)
    **Sr. ASIC Engineer ** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a ... service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon… more
    Cisco (12/03/25)
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  • Sr. SOC/ ASIC Physical Design…

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
    SpaceX (12/11/25)
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  • Sr. ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX...to solve complex problems including clock domain crossings and power optimization + ASIC /SoC system integration experience… more
    SpaceX (11/20/25)
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  • ASIC /SOC DFT Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    ASIC /SOC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... make this possible, with the ultimate goal of enabling human life on Mars. ASIC /SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
    SpaceX (09/18/25)
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  • ASIC Digital Design Engineer

    Teledyne (Goleta, CA)
    …of being on a team that wins. **Job Description** **Job Summary:** ASIC Digital Design Engineer : Oversees definition, design, verification, and documentation ... windowing). + Finite State Machine and datapath design for ASIC modes. + Clock domain crossing and power... ASIC modes. + Clock domain crossing and power -aware RTL coding (asynchronous resets, and multi-clock domains). +… more
    Teledyne (11/21/25)
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  • ASIC Engineer , Formal Verification

    Meta (Sacramento, CA)
    …Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide technical ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the...clock domain crossing, IP-XACT based register verification and low power 22. Experience with development of fully automated flows… more
    Meta (10/20/25)
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  • ASIC Engineer , Physical Design

    Meta (Sunnyvale, CA)
    …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... physical design of an end-to-end IP or integration of ASIC /SoC design and point out lower power ...of ASIC /SoC design and point out lower power and higher performance trade-offs 4. Define and implement… more
    Meta (11/05/25)
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