• ASIC Implementation Engineer

    Meta (Sunnyvale, CA)
    … Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform ... technical field, or equivalent practical experience 9. 6+ years of experience in static verification tools 10. Experience with Lint, Clock Domain & Reset Domain… more
    Meta (06/25/25)
    - Related Jobs
  • Static Timing Analysis Engineer

    Google (Mountain View, CA)
    …with high complexity silicon in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis. + ... and associated automation. + Experience in one or more static timing tools (eg, PrimeTime, Tempus). Preferred qualifications: +...and their tradeoffs. + Drive clock tree planning and implementation for SoCs to achieve best energy, performance and… more
    Google (06/21/25)
    - Related Jobs
  • ASIC and/or FPGA Design & Verification…

    The Boeing Company (Huntington Beach, CA)
    …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will develop ... of ASIC /FPGA design or verification experience + Experience with ASIC /FPGA architectural definition, and detailed design implementation and functional… more
    The Boeing Company (06/20/25)
    - Related Jobs
  • Sr. SOC/ ASIC Physical Design…

    SpaceX (Sunnyvale, CA)
    …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC more
    SpaceX (06/19/25)
    - Related Jobs
  • ASIC Engineer , Physical Design

    Meta (Sunnyvale, CA)
    …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
    Meta (06/14/25)
    - Related Jobs
  • ASIC Design Engineer

    Broadcom (San Jose, CA)
    …be challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from ... marketing/system requirements, RTL design and verification, synthesis, static timing analysis. You will either be responsible for block and/or chip level design and… more
    Broadcom (04/26/25)
    - Related Jobs
  • Senior ASIC Physical Design and Timing…

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and… more
    NVIDIA (06/10/25)
    - Related Jobs
  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are ... of DFT/Test timing such as timing constraints, timing analysis, timing convergence, and ECO implementation . What we need to see: + Hold a BS in Electrical or… more
    NVIDIA (06/10/25)
    - Related Jobs
  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... timing constraints, driving timing and power convergence, as well as ECO implementation + Apply knowledge and experience to improve timing convergence flows working… more
    NVIDIA (06/17/25)
    - Related Jobs
  • Senior High-Performance ASIC Timing…

    NVIDIA (Santa Clara, CA)
    …generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You will be ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and timing methodologies. + Finding the right tradeoffs and balance… more
    NVIDIA (06/24/25)
    - Related Jobs