- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... and/or full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, … more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If ... timing such as timing constraints, timing analysis, timing convergence, and ECO implementation . What we need to see: + Hold a BS in Electrical or… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... timing and power convergence, as well as ECO implementation + Apply knowledge and experience to improve ...implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What… more
- NVIDIA (Santa Clara, CA)
- …for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation , and timing methodologies. + ... MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience...Timing + Hands-on experience in STA tools, ECO implementation , and timing closure of high-speed designs.… more
- Meta (Menlo Park, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure...optimization techniques and generate optimized Gate Level Netlist for Timing , Area, Power 2. Debug the timing /area/congestion… more
- Meta (Sunnyvale, CA)
- … Implementation Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification ... TCL, and Make 17. Experience with SOC Design Integration and Front-End Implementation 18. Knowledge of Timing /physical libraries, SRAM Memories 19. Experience… more
- Broadcom (San Jose, CA)
- …major segments of the Semiconductor industry, including AI. Be part of the Design Implementation team within Broadcom ASIC Products Division where we create CMOS ... concept through product release. Become a member of an ASIC design team responsible for all aspects of physical...- Floor planning chips and blocks - Routing - Timing , both mission mode and test modes - Integration… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC… more
- SpaceX (Irvine, CA)
- …FPGA design flow (eg synthesis, timing closure, verification) + Work with ASIC backend/ implementation teams as needed + Bring-up and validate ASICs and FPGAs ... FPGA/ ASIC Design Engineer (Silicon Engineering) Irvine,...cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will… more