• Amazon (Cupertino, CA)
    …to you - come build the future with us! Key job responsibilities *Perform physical design for Amazon's machine learning custom silicon solutions *Participate in ... various aspects of physical design : full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route, power integrity… more
    Upward (07/12/25)
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  • Celestial AI (Santa Clara, CA)
    …memory, assembly, and packaging suppliers. ABOUT THE ROLE We are looking for a Senior ASIC /VLSI Synthesis and Design Engineer to drive the development of ... power analysis. If you have a strong background in ASIC /VLSI design , with deep expertise in synthesis,...area issues, ensuring efficient and scalable designs. Collaborate with physical design teams to ensure smooth handoff… more
    Upward (07/18/25)
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  • Capgemini (San Francisco, CA)
    About the job you're considering We are seeking a skilled CAD Infrastructure engineer to support our ASIC design team. The ideal candidate will be ... scripting Knowledge of industry standards and best practices in ASIC design . This role is crucial for...digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of… more
    Upward (07/21/25)
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  • DBSI Services, Inc. (Milpitas, CA)
    Benefits: 401(k) 401(k) matching Relocation bonus Job Title: Physical Design Engineer Location: Milpitas, CA Primary Responsibilities: Pre-layout STA to ... years of experience or equivalent experience. MSEE preferred. Experience in ASIC Physical Design ; Experience in an SoC product developmentorganization with… more
    Upward (06/27/25)
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  • Neuralink (Fremont, CA)
    …what is possible today and define the future. Job Responsibilities and Description: The Physical Design and Verification Engineer will be responsible for RTL ... or equivalent experience. Experience working on physical design and implementation of complex ASIC systems...physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and… more
    Upward (07/11/25)
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  • Tesla Motors (Palo Alto, CA)
    Tesla's Infotainment Team is seeking a detail-oriented and enthusiastic Electronic Design Engineer with a strong background in computer system architecture, ... and manufacturing support for Infotainment Systems. This Sr. Electronic Design Engineer , Infotainment will be responsible for...and power integrity Experience with schematic capture and PCB physical design using Cadence Concept and Allegro… more
    Upward (07/19/25)
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  • TrellisWare Technologies, Inc (San Diego, CA)
    …much at stake to go solo. Our Engineering Team is seeking a hybrid Digital Design Engineer . You would be responsible for the architecture, design , ... modules and systems in VHDL. Simulates both modules and systems. Generates required design documentation. Synthesizes VHDL to FPGA and/or ASIC . Integrates and… more
    Upward (07/01/25)
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  • Microchip Technology (San Jose, CA)
    …integrations into Microchip FPGA products Work on architecture & implementation for Analog, ASIC & FPGA design development, integration, and deployment for high ... People come to work at Microchip because we help design the technology that runs the world. They stay...disciplines 12+ years of industrial experience Proven experience in ASIC & FPGA IP development, integration, and deployment, including… more
    Upward (07/23/25)
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  • Advanced Micro Devices, Inc (San Jose, CA)
    …of diverse perspectives. AMD together we advance_ THE ROLE: AMD is seeking a ASIC Design Engineer with specific experience with scripting skills around ... timing analysis. He/She will also develop parsers to extract and waive key design metrics from industry standard synthesis and timing reports. These metrics are… more
    Upward (07/01/25)
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  • Advanced Micro Devices, Inc (Santa Clara, CA)
    …diverse perspectives. AMD together we advance_ THE ROLE: As a Signal Integrity Engineer in Networking Technology & Solutions Group (NTSG), you will be responsible ... role, you will closely collaborate with Silicon IP team, ASIC packaging team, PCB team, System Architect and external...to validate the channel health for IEEE compliance Execute Design of Experiments (DOE) sweeping to statistically evaluate the… more
    Upward (07/10/25)
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