- Google (Sunnyvale, CA)
- …measuring chip power consumption. + Develop design improvements to increase power efficiency . + Collaborate with cross-functional teams in defining power ... using EDA tools such as PTPX, PowerArtist, or PrimePower. + Experience driving power - efficiency improvement in chip designs. + Experience with pre-silicon vs… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on ... to extend the state of the art performance and efficiency + You are expected to understand the design...are expected to understand the design and implementation, develop power metrics and drive power reductions +… more
- Qualcomm (San Diego, CA)
- …**General Summary:** Qualcomm mixed-signal IP design team is seeking talented senior ASIC digital designers to join our efforts in developing the next generation ... - Apply computer architecture and optimization techniques for improving power , performance, and area of the IPs - Assist...- Assist in running the full suite of front-end ASIC design tools (lint checking, CDC, DFT, synthesis, FV,… more
- Google (Sunnyvale, CA)
- …experience with System Level Test or System validation. + Experience with ASIC or SoC prototype bring-up, debug, functional verification, or functional manufacturing ... process, Kernel, and CPU performance. + Experience implementing secure ASIC /SoC manufacturing solutions (provisioning, e-fuse programming, or life-cycle management).… more
- Qualcomm (Santa Clara, CA)
- …of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such ... model development and formal verification (property checking). Learn and deploy power -aware UPF verification flow and methodology. Involve in developing automation… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to ... Computer Architecture and Digital Systems design. + A deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis,… more
- NVIDIA (Santa Clara, CA)
- …Design Verification Engineers with a specialty in tools and automation to drive efficiency and collaboration among our High Speed IO engineering teams. This position ... of relevant industry experience + Exposure to computer architecture, ASIC design, and verification methodology is required + Experience...the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear… more
- Google (Mountain View, CA)
- …+ Experience with logic synthesis techniques to improve RTL code, performance and power as well as low- power design techniques. + Experience with ARM-based ... SoCs, interconnects and ASIC methodology. + Experience with a scripting language like...interconnects or peripherals. + Experience with methodologies for low power estimation, timing closure, or synthesis. + Experience with… more
- Google (Sunnyvale, CA)
- …specific focus on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Design Verification Engineer , you will be part of a team ... team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to...use Google services around the world. We prioritize security, efficiency , and reliability across everything we do - from… more
- Google (Mountain View, CA)
- …like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: + Master's degree or PhD in Electrical ... industry experience with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with methodologies for RTL… more