• ASIC SoC System Level…

    Google (Sunnyvale, CA)
    …or a related field, or equivalent practical experience. + 2 years of experience with System Level Test (SLT) or product engineering. + Experience with ASIC ... benefits. Learn more about benefits at Google. + Develop System Level Test (SLT) solutions for custom... Test (SLT) solutions for custom Application-Specific Integrated Circuits ( ASIC ) and SoC 's by specifying hardware and… more
    Google (07/09/25)
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  • Sr. SOC / ASIC Physical Design…

    SpaceX (Sunnyvale, CA)
    Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
    SpaceX (06/19/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    … ASIC Design Engineers to design and implement the world's leading GPU and SoC 's. With the System - ASIC team, you will contribute to designing multiple ... ASIC designers, and verification engineers to design sophisticated system - level modules such as Floorsweep, In-silicon measurement,...teams in the silicon bring-up process and ensure successful SOC level integration. + You will also… more
    NVIDIA (06/19/25)
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  • Senior Reset and Boot ASIC Engineer

    NVIDIA (Santa Clara, CA)
    … ASIC Design Engineers to design and implement the world's leading GPU and SoC 's. With the System - ASIC team, you will contribute to designing multiple ... architects, ASIC designers, and verification engineers to design sophisticated system - level modules such as Floorsweep, In-silicon measurement, Reset and… more
    NVIDIA (06/18/25)
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  • FPGA/ ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    …curious engineer who will work alongside world-class cross-disciplinary teams ( systems , firmware, architecture, design, validation, product engineering, ASIC ... RTL in Verilog or SystemVerilog + Experience in designing SoC , DSP, digital communication system datapath blocks,...and weekends as needed COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Level I: $120,000.00 - $145,000.00/per… more
    SpaceX (06/12/25)
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  • ASIC Design Engineer - New College Grad

    NVIDIA (Santa Clara, CA)
    … System - level modules. What you'll be doing: + Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs ... self-driving cars and the growing field of artificial intelligence. System - ASIC team works closely with System...teams in the silicon bring-up process and ensure successful SOC level integration. + You will also… more
    NVIDIA (06/28/25)
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  • ASIC Engineer, Design Verification

    Meta (Menlo Park, CA)
    …Chip ( SoC ) verification plans, build verification test benches to enable block/IP/sub- system / SoC level verification 2. Develop functional tests based on ... SystemVerilog/UVM methodology or C/C++ based verification 8. 3+ years experience in block/IP/sub- system and/or SoC level verification based on SystemVerilog… more
    Meta (07/11/25)
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  • ASIC Engineer, Design Verification

    Meta (Menlo Park, CA)
    …implement IP/ SoC verification plans, build verification test benches to enable IP/sub- system / SoC level verification 2. Develop functional tests based on ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization....and/or C/C++ based verification 10. 8+ years experience in IP/sub- system and/or SoC level verification… more
    Meta (07/11/25)
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  • ASIC Engineer, Design Verification

    Meta (Menlo Park, CA)
    …implement IP/ SoC verification plans, build verification test benches to enable IP/sub- system / SoC level verification 2. Develop functional tests based on ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization....C/C++ based verification 9. 6+ years of experience in IP/sub- system and/or SoC level verification… more
    Meta (07/11/25)
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  • Sr. ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    …to solve complex problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with multicore CPU ... curious engineer who will work alongside world-class cross-disciplinary teams ( systems , firmware, architecture, design, validation, product engineering, ASIC … more
    SpaceX (06/12/25)
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