• CPU Core Logic Designer

    Intel Corporation (Folsom, CA)
    design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. + Reviews the verification plan and ... C, C++, C#, Visual Basic/.NET. Perl, Python, Java, etc.). + Modern energy-efficient/ low -power logic design techniques, including those specifically applicable to… more
    Intel Corporation (12/17/25)
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  • Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...track record of PPA improvement on high performance and low power designs in advanced technology nodes + Strong… more
    NVIDIA (11/19/25)
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  • Manager, Hardware Design Engineering

    Celestica (San Jose, CA)
    … for leading edge high speed communication devices + Experience in power supply design for sensitive optical, switch, memory, NPU, CPU , GPU components + Failure ... Country: USA State/Province: California City: San Jose **Summary** The Manager, Hardware Design (Power) Engineering is responsible for leading and managing the work… more
    Celestica (10/16/25)
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  • Principal ASIC Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …and power optimization + Experience developing complex ASICs + Experience with multicore CPU subsystem design + Experience with standard bus protocols (eg AXI, ... Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check) +...with embedded processors + Experience with high speed and low power design techniques + Scripting skills… more
    SpaceX (12/22/25)
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  • Senior Engineer, Front End Computer Aided…

    Microsoft Corporation (Mountain View, CA)
    …hand-off to backend and Logic Design compilation, elaboration in addition to experience in Low Power design . - 5+ years of experience in digital design ... Python OR equivalent experience. - 10+ years of relevant experience. - Expertise in CPU /SoC design principles. - For Front-End Handoff CAD Roles: - In-depth… more
    Microsoft Corporation (12/03/25)
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  • Principal, Design Engineering

    Celestica (San Jose, CA)
    …California City: San Jose **General Overview** **Job Title:** Principal, Design Engineering **Functional Area:** Engineering (ENG) **Career Stream:** Engineering ... reviews in areas such as manufacturing, test, supply chain, reliability, industrial design and simulations. **Detailed Description** Performs tasks such as, but not… more
    Celestica (11/07/25)
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  • Lead Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …in one or more of these areas: + Synthesis, DFT, Logical Equivalency Checking + Low Power Design Implementation, SDC Verification + Place and Route + Parasitic ... of technology. Cadence is a pivotal leader in electronic design , building upon more than 30 years of computational...projects in areas such as 5G, IOT, automotive, advanced CPU , wireless, audio, image processing, AI, machine learning etc.… more
    Cadence Design Systems, Inc. (12/03/25)
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  • Hardware Engineer

    Cisco (Milpitas, CA)
    …crypto accelerators and network processing units, to deliver exceptional throughput, low latency, and robust security features. **Your Impact** We are looking ... for a skilled and proactive FPGA Design Engineer with 3+ years of industry experience to...interfaces between the FPGA and other system components (eg, CPU , memory, sensors). + Hardware Debugging: Lead debugging efforts… more
    Cisco (12/16/25)
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  • Engineer VII

    General Atomics (San Diego, CA)
    …staff and chief engineers in the concept development, architecture, and prototype design , integration, and test of high-power processing solutions for all product ... latitude in determining technical objectives for the review, research, design , development, and/or solutions for designated engineering systems, projects, and… more
    General Atomics (12/11/25)
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  • Engineering Team Lead, Aladdin Engineering - Vice…

    BlackRock (Santa Monica, CA)
    …( low /no GC, off-heap caching, kernel bypass, cache locality, CPU pinning, Linux customizations). + Experience with optimization, algorithms, or quantitative ... as Vice President, AXE/IOI Engineering Team Lead, where you will lead the design , development, and evolution of our IOI (Indication of Interest) and AXE… more
    BlackRock (01/06/26)
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