• CPU Power Analysis…

    Qualcomm (Santa Clara, CA)
    …Engineering Group, Engineering Group > CPU Engineering **General Summary:** + Drive Power analysis and Projections on a project involved in the development ... of CPUSS with emphasis in power analysis . + Define CPU rail planning and PMIC inductor sizing working closely with SoC and Board teams + Work with CPU ,… more
    Qualcomm (07/16/25)
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  • Lead CPU Performance Analysis…

    Qualcomm (Santa Clara, CA)
    …**Job Area:** Engineering Group, Engineering Group > SoC Architecture **General Summary:** As a Lead CPU Performance Analysis Engineer, you will be working ... on CPU performance analysis and tuning, microbenchmark development, workload characterization, workload tracing, and performing competitive performance … more
    Qualcomm (06/21/25)
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  • CPU Physical Design - Low Power…

    Qualcomm (San Diego, CA)
    …CLP and FV signoff from synthesis to PNR exit. + Signoff knowledge is mandatory (STA, Power analysis ,FV, low power verification, PV,etc) + Quick learner with ... a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central...verification, STA, Physical design, etc. + Knowledge of low power flow ( power gating, multi-Vt flow, … more
    Qualcomm (06/05/25)
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  • Lead CPU Performance Architect,…

    Google (Mountain View, CA)
    …hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Lead CPU Performance Architect in architecture and performance, you ... design. + Experience in CPU architecture with CPU blocks. + Experience in performance modeling, analysis...both architecture and performance angles. + Define and write CPU subsystem architecture specifications. + Lead the… more
    Google (06/21/25)
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  • CPU Architecture Lead

    Google (Mountain View, CA)
    …of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Lead CPU Architect in architecture and performance, you will be ... analysis , correlation, and workload characterization. + Experience in CPU architecture with CPU blocks, and with...microarchitecture concepts. + Collaborate with design teams in Performance, Power , Area (PPA) tradeoff analysis for new… more
    Google (06/21/25)
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  • Senior CPU Architecture and Performance…

    Google (Mountain View, CA)
    …performance and design. + Experience in high-performance CPU architecture and CPU blocks. + Experience in performance modeling, analysis , correlation, and ... leadership, you will be planning a project and guiding CPU architects and working with engineers in power...both architecture and performance angles. + Define and write CPU subsystem architecture specifications. + Lead the… more
    Google (06/26/25)
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  • CPU Floorplan and Integration Engineer, San…

    Qualcomm (Santa Clara, CA)
    …Minimum Requirements + Proficiency in synthesis, place and route, and signoff timing/ power analysis . + Expertise in block-level implementation as well as ... physical design teams to design, floorplan and integrate the CPU designs meeting aggressive power , area and...is strongly preferred. + Experience as a key technical lead driving development and delivery of physical design databases… more
    Qualcomm (06/05/25)
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  • CPU Physical Design Pathfinding Engineer

    Qualcomm (San Diego, CA)
    …Must have skill/experience + Experience with Synthesis, place and route and signoff timing/ power analysis . + Knowledge of high performance and low power ... **Company:** Qualcomm Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CPU PPA Pathfinding… more
    Qualcomm (07/03/25)
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  • Senior Silicon Power Performance Engineer

    NVIDIA (Santa Clara, CA)
    …(SSG) is where innovation meets impact. Our mission is to craft outstanding GPU CPU and SoC products that power Artificial Intelligence, Gaming, Virtual Reality, ... and SOC products. In this position, you will: + Lead multi-functional teams to validate implement silicon power... and optimization. + Exposure to digital design, circuit analysis , CPU /GPU/SOC architecture, PTPX, process technologies and… more
    NVIDIA (06/13/25)
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  • Failure Analysis Technical Lead

    Cisco (San Jose, CA)
    Failure Analysis Technical Lead Apply (https://jobs.cisco.com/jobs/Login?projectId=1441361) + Location:San Jose, California, US + Area of InterestSupply Chain + ... learning information quickly and uses resources to research and resolve issues. + Failure Analysis Technical Lead will drive the improvements in the accuracy of… more
    Cisco (06/25/25)
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