- Broadcom (San Jose, CA)
- …candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network switch/routing designs. The ... and routing ASICs and various subsystems within these chips. 2). Doing chip level integration and putting all the functional blocks, soft/hard IPs, IOs, and… more
- Renesas (Goleta, CA)
- Senior Device Design & Integration Engineer Job Description This role will work in our Device and Product Group supporting New Technology Introduction (NTI) of ... our next-gen GaN semiconductor devices. The engineer will be responsible for high-voltage device design (including epi materials), chip layout, FET selection,… more
- Renesas (Goleta, CA)
- Staff Device Design & Integration Engineer Job Description This Device Design and Integration Engineer will work on the design and the implementation of ... for the choice of GaN epitaxial structures, the device dimensions, the chip layout and package considerations to meet cost, performance and reliability… more
- Cisco (Carlsbad, CA)
- …provide a unique opportunity to seek modes of improvement that span from photonic chip design to optical assembly (ie, integration of fibers, light sources, ... part of a world class photonics team on the integration of Cisco's silicon photonics into our automated, high-volume...photonics manufacturing platform. Who You Are: You are an engineer or scientist with experience in one or more… more
- NVIDIA (Santa Clara, CA)
- …and help define the future of computing. We seek an experienced Post-Silicon Hardware Engineer to join our Silicon Solutions Group. In this role, you will validate ... meet aggressive schedules. + Cross-Functional Impact - Partner with architects, chip /board designers, firmware/software engineers, and QA to drive design, debug, and… more
- Google (Sunnyvale, CA)
- …its integration within AI/ML-driven systems. As a Signal Integrity/Power Integrity Engineer , you will lead chip and package design, ensuring optimal Signal ... Signal and Power Integrity Engineer , PhD, University Graduate _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving… more
- Google (Sunnyvale, CA)
- …shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration . As a Chip Package Designer on the Silicon ... Package Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid**...equivalent practical experience. + 4 years of experience in chip package substrate design using Cadence APD (Allegro Package… more
- Google (Sunnyvale, CA)
- …10 years of experience in physical design (eg, with a focus on floorplanning, integration , or top-level chip assembly). + Experience in physical design working ... SoC Silicon Top-Level Floorplan Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Advanced**...timing/congestion closure for complex modern SoCs. You will utilize full- chip planning and IP integration , delivering floorplan… more
- Meta (Sunnyvale, CA)
- …or block level uArchitecture definition and RTL implementation 2. Contribute to chip -level integration , verification plan development and verification 3. Define ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work...static timing analysis 4. Support the test program development, chip validation and chip life until production… more
- NVIDIA (Santa Clara, CA)
- We are looking to hire a Chip Design Verification Engineer to join NVIDIA Chip Design group. The work environment is versatile, educational, dynamic and ... AI data centers. We are seeking a senior verification engineer to help us ensure the quality and correctness...own verification strategy and execution from the block-level through full- chip (SoC) integration . + Sharp analytical and… more