• DDR PHY Timing Design…

    Qualcomm (San Diego, CA)
    …position requires involvement in static timing analysis (STA) and closure of DDR PHY interface and internal logic components operating on high speed ... **Responsibilities include:** + Focused analysis and ownership of specific DDR PHY architecture components for timing...Good understanding of architecture, system, and integration aspects for DDR PHYs. + Good understanding of design … more
    Qualcomm (06/27/25)
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  • Lpddr Phy System Design Engineer

    Qualcomm (San Diego, CA)
    …Engineering Group, Engineering Group > ASICS Engineering **General Summary:** Join the LPDDR PHY design team at the forefront of developing high-speed, low-power ... **Responsibilities** : + Drive the analysis and architectural ownership of LPDDR PHY systems. + Develop comprehensive system timing budgets, encompassing both… more
    Qualcomm (07/02/25)
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  • Sr. HBM PHY Expert, Annapurna Labs

    Amazon (Cupertino, CA)
    … DDR /HBM at the PHY and controller level - Good knowledge of DDR /HBM training, timing parameters and/or controller features - Drive the IP Integration and ... customers change the world. We are seeking an HBM/DDRx Phy expert with role in the definition, design...of silicon and 2.5D packaging - Support the physical design team, review clocking and timing constraints… more
    Amazon (06/06/25)
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  • Signal and Power Integrity Engineer (Multiple…

    Qualcomm (Santa Clara, CA)
    …driving JEDEC or similar standardization is a plus **Preferred Qualifications:** + Experience in DDR design specifications such as DDR and LPDDR + Experience ... **Minimum Qualifications:** + 8+ years of experience with 5+ years in DDR /SerDes in Package/PCB/System Design related to compute/server standards. + Experience… more
    Qualcomm (06/20/25)
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  • SMTS - High Bandwidth Memory Input Output (I/O)…

    Micron Technology, Inc. (Folsom, CA)
    …of high speed I/O design + Hands on experience in High-Speed IO PHY architecture definition + Proven understanding of industry HSIO protocols like DDR , PCIe, ... years of experience in memory address and data path architecture/ design + 5+ years of experience in system ...design + 5+ years of experience in system timing budgeting + Deep understanding of signal integrity, channel… more
    Micron Technology, Inc. (06/18/25)
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  • Senior Silicon Engineer

    Microsoft Corporation (Santa Clara, CA)
    …plans and methodology. + Collaborate with Physical design teams to ensure design meets timing and area requirements. + Work on post-silicon verification and ... + Own the micro-architecture specification and RTL development of design modules for ASIC memory subsystem. + Review and...Hands-on experience in integrating 3rd party IP, such as DDR Controller/ PHY and PLLs. + Proven experience… more
    Microsoft Corporation (07/04/25)
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