• DFT Quality Engineer

    Broadcom (San Jose, CA)
    …already have a Candidate Account, please Sign-In before you apply.** **Job Description:** ** DFT Quality Engineer ** Broadcom's ASIC Product Division is ... seeking candidates for a DFT Quality Engineer position at our San Jose design center in CA. In this role, you will play a crucial part in ensuring the … more
    Broadcom (12/12/25)
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  • SoC DFT Engineer , Google Cloud

    Google (Sunnyvale, CA)
    SoC DFT Engineer , Google Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more ... architecture and its integration within AI/ML-driven systems. As a DFT Engineer you will be responsible for...responsible for diagnosing memory and logic failures, increasing production quality , and enhancing yield and reducing test cost. The… more
    Google (11/25/25)
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  • HBM/DDR/SerDes DFT Verification Lead…

    Broadcom (San Jose, CA)
    …San Jose, California Development Center. We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role, you ... highest quality standards. **Key Responsibilities:** + Implement and verify DFT methodologies specifically for HBM, DDR and SerDes designs. + Collaborate with… more
    Broadcom (12/06/25)
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  • Staff DFT Engineer

    Broadcom (San Jose, CA)
    …apply.** **Job Description:** Broadcom's CSG division is seeking candidates for a Staff DFT engineer position. The successful candidate will be responsible for ... DFx solutions while optimizing the cost for test. **Responsibilities** + Own IP DFT architecture, implementation, verification, signoff STA constraints for DFT +… more
    Broadcom (11/26/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most ... network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. .… more
    Broadcom (11/19/25)
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  • ASIC/SOC DFT Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    ASIC/SOC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're...+ Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals… more
    SpaceX (09/18/25)
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  • Senior Principal DFT Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …an impact on the world of technology. We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and ... (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly...SoC/ASIC Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT more
    Cadence Design Systems, Inc. (10/30/25)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire ... internal CAD teams to drive scalable, automated solutions. + Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the boundaries… more
    NVIDIA (10/17/25)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the ... + In addition, you will help develop and deploy DFT methodologies for our next generation products. + You...engineers on test designs and trade-offs including cost and quality . What we need to see: + BSEE (or… more
    NVIDIA (10/29/25)
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  • Senior DFT Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …also help mentor junior engineers on test designs and trade-offs including cost and quality . What we need to see: + BSEE (or equivalent experience) with 5+ years, ... years, or PhD with 2+ years of experience in DFT , system architecture, or RTL design. + Understanding of...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
    NVIDIA (10/17/25)
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