- Capgemini (San Francisco, CA)
- …_ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification ( DV ) Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:** ... **Job description:** Analog/Mixed-Signal Design Verification **Key responsibilities:** + Extract...Develop timing model for the circuit working with layout engineer . + This role will provide the ability to… more
- Cisco (San Jose, CA)
- …and Verification teams and Architects to understand chip architecture and drive design verification requirements. You'll work with SDK and Software teams as ... ASIC in deployment-mode applications * You will participate in the ASIC design verification and Emulation for Cisco high-end switching products. One of the… more
- Amazon (San Diego, CA)
- …technologies. In this role you will: . Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models . ... be reused for the ASIC implementation . Run formal verification of complex blocks to ensure functional correctness ....blocks to ensure functional correctness . Work with the design and communication systems team and participate in system… more
- Micron Technology, Inc. (San Jose, CA)
- …models (LLMs) for the purpose of automated Silicon design and Design Verification ( DV ). The engineer is expected to build LLM based EDA workflows ... which assists the Design Engineers in building the next Micron product at...LLMs for the purpose of automated corner case uncovering, design optimization and spec-to- design translation. + Develop… more
- Qualcomm (Santa Clara, CA)
- …**Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** As a Design Verification Lead, you will lead a team of ASIC design ... a team defining the processes, methods and tools for design verification of large complex IP blocks...+ 8+ years or more of practical semiconductor ASIC DV experience including owning end-to-end verification of… more
- Capgemini (San Jose, CA)
- …_Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Mixed-Signal Design Verification Engineer_ **Location:** ... **Job Role: Senior** **Mixed Signal DV Engineer ** **Job Location: San Jose...This role will provide the ability to directly influence design related changes as required to meet functional specifications.… more
- BAE Systems (San Diego, CA)
- …Other incentives may be available based on position level and/or job specifics. ** Design Verification Engineer - FPGA - (Sign-on Bonus)** **112648BR** ... career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect,...your leadership skills while leading small to medium sized DV teams + Create reusable Verification IP… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer , you will ... towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1....7. Experience in verifying a IP block using standard DV based techniques. 8. Experience in EDA tools and… more
- Qualcomm (Santa Clara, CA)
- …This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification ... flow and methodology. Involve in developing automation to improve verification efficiency. **Qualifications:** + DV experience using uvm/assertion based… more
- BAE Systems (San Diego, CA)
- …Other incentives may be available based on position level and/or job specifics. **Senior Design Verification Engineer - FPGA** **110464BR** EEO Career Site ... advancing your career. BAE is looking for experienced FPGA Design Verification Engineers who can develop and...evolution of our processes and methodologies. + Enhance your DV skills as well as your knowledge of Electronic… more