- NVIDIA (Santa Clara, CA)
- We are now seeking a Formal Verification Engineer , focusing on the firmware verification ! In this role, you will be instrumental in ensuring the ... applying advanced formal methods to solve complex firmware verification and hardware- firmware co-... co- verification challenges at scale. As a Formal Verification Engineer , your primary… more
- Northrop Grumman (San Diego, CA)
- …integration testing with embedded processors and avionics systems + Participate in formal verification and validation activities + Synthesis, Place & Route, ... **Northrop Grumman Aeronautics Systems** has an opening for a **Sr. Principal** ** Firmware ** ** Engineer ** to join our team of qualified, diverse individuals… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Chip (SoC) for data center applications. As a Design Verification Engineer , you will be part of...or more of the following areas along with functional verification -SV Assertions, Formal , Emulation 12. Experience in… more
- Meta (Sunnyvale, CA)
- …through architecture, firmware , and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement IP/SoC ... verification plans, build verification test benches to enable IP/sub-system/SoC level ...or more of the following areas: SystemVerilog Assertions (SVA), Formal , and Emulation 15. Prior working knowledge of Audio/image/Video… more
- Meta (Sunnyvale, CA)
- …through architecture, firmware , and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement verification ... plans, and build test benches for block, IP, sub-system, and SoC level verification 2. Develop functional tests based on verification test plan 3. Drive Design … more
- Capgemini (Santa Clara, CA)
- …(Python, TCL). + Strong grasp of **functional coverage** , simulation, emulation, and formal verification . + Proven ability to **lead teams** , **influence ... verification environments** leveraging UVM, UPF, and advanced methodologies. ** Engineer tailored solutions** that align with client objectives and industry best… more
- SpaceX (Sunnyvale, CA)
- …of design blocks using Verilog/SystemVerilog + Familiar with UPF (unified power format), formal verification , and DRC rule checking experience + Ability to work ... hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer /Level I: $130,000.00 - $155,000.00/per year Design … more
- Northrop Grumman (Los Angeles, CA)
- …etc. + Generation of complex test benches in Modelsim or Questasim to support formal Verification . + Familiarity with the VxWorks RTOS, its architecture and ... Defense Systems has an opening for a **Staff FPGA (DSP) Digital Design Engineer ** with an active clearance, to join our team of qualified, diverse individuals.… more
- Northrop Grumman (Los Angeles, CA)
- …Experience in Test script development with HW interfaces + Experience performing formal requirements decomposition and/or verification + Works under only general ... Grumman Mission Systems is searching for a **Sr. Principal Engineer Embedded Software** to support our Software and Test...software issues to support subsystem and system level Design Verification Tests (DVTs). + Communicate SW project status to… more
- Northrop Grumman (Los Angeles, CA)
- …oscilloscopes and logic analyzers. + Generation of Test Benches and support of formal VHDL Verification Primary Level Salary Range: $101,000.00 - $151,400.00 The ... to landing on the moon. We are currently seeking a **FPGA Digital Design Engineer (Level 02)** for our tactical missile system development and production programs at… more