- NVIDIA (Santa Clara, CA)
- …design and verification methodology is required + Strong ability with SystemVerilog , test planning, coverage closure, and test bench design + Understanding of ... with assertion-based verification , Semiformal Verification (SFV), Unified Verification Methodology (UVM), SystemVerilog checkers and scoreboards. + Perl… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement ... joining Meta 7. 2+ years of hands-on experience in SystemVerilog /UVM methodology or C/C++ based verification 8....verifying ARM/RISC-V based sub-systems and SoCs 14. Experience verifying CPU/ GPU designs 15. Experience in one or more of… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...practical experience 8. 6+ years of hands-on experience in SystemVerilog /UVM methodology and/or C/C++ based verification 9.… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Chip (SoC) for data center applications. As a Design Verification Engineer , you will be part of...development cycles 9. 8+ years of hands-on experience in SystemVerilog /UVM methodology and/or C/C++ based verification 10.… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Chip (SoC) for data center applications. As a Design Verification Engineer , you will be part of...development cycles 9. 8+ years of hands-on experience in SystemVerilog /UVM methodology and/or C/C++ based verification 10.… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Join us today! We are now looking for a Senior System Verification Engineer to join our Emulation division and will be working onsite ... should be proficient in Verilog and/or VHDL, C/C++ and SystemVerilog . + Protocol knowledge of at least one of...in server platforms + Working Knowledge of CPU - GPU coherency + Experience with UVM verification … more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal ... Chip (SoC) for data center applications. As a Formal Verification Engineer , you will be part of...teams 15. Fluency in hardware description languages, such as SystemVerilog and SVA 16. Proficiency in scripting languages such… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Verification Engineer to join our Emulation division. We are a worldwide recognized division noted for groundbreaking technology. We are ... work-flex, family and diverse team! NVIDIA invention of the GPU in 1999 accelerated the growth of the PC...should be proficient in Verilog and/or VHDL, C/C++ and SystemVerilog . + Experience with UVM verification environments… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking outstanding Verification Engineers with a specialty in tools and automation to drive efficiency and collaboration among our High Speed IO ... to artificial intelligence to self-driving cars and supercomputers. Our verification infrastructure and methodology team automates, analyzes, and optimizes the… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC...next generation GPUs + Partner with RTL and Design Verification engineers to ensure delivery meets performance and quality… more
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