• High Speed RTL Design

    Broadcom (San Jose, CA)
    …If you already have a Candidate Account, please Sign-In before you apply.** **Job Description:** High Speed RTL Design Engineer Qualifications include: + ... or Computer Engineering with 10+ years of experience in RTL design . + Proficient with Verilog-HDL/System Verilog...understanding of Signal Integrity and Power Integrity modeling for High Speed designs. - Understanding & exposure… more
    Broadcom (05/08/25)
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  • Senior Digital ( RTL ) Design

    Capgemini (San Francisco, CA)
    … Engineer** **Job Location:** **San Francisco CA** **Job Description** We are seeking Digital Design / RTL Design engineer for our Full Time Employment with ... Experienced at modeling complex state machines, data-paths, and bus protocols/ High speed (bandwidth) interfaces such as PCIe,...5 to 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog… more
    Capgemini (04/29/25)
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  • DSP or Serdes RTL Lead Digital…

    Cadence Design Systems, Inc. (San Jose, CA)
    …SerDes exp.) will be considered. Position Requirements This team is focused on DSP and/or High Speed Serdes . The ideal candidate will have at least 3 plus ... join a dynamic and growing team of engineers developing high - speed PMA layer IP for industry-standard protocols....limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification… more
    Cadence Design Systems, Inc. (05/08/25)
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  • Next-Gen, High - Speed Memory…

    Qualcomm (San Diego, CA)
    … Team is looking for ASIC Design Engineers for the next generation high speed LPDDR/DDR memory subsystems.. The front end of the DDR controller interfaces ... RTL coding), and deployment of the next generation, high - speed memory subsystems into QCT products. You...Engineering and at least 5+ years of experience in high speed digital design Master's… more
    Qualcomm (02/19/25)
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  • Digital ASIC Design Engineer…

    Qualcomm (San Diego, CA)
    …- Work with cross functional team for architecture definition of the high - speed interfaces - Define, document and design the microarchitecture of IP blocks ... join our efforts in developing the next generation of high - speed interfaces. These interfaces include SerDes, DDR,...- Own the RTL design for the IP blocks and… more
    Qualcomm (04/19/25)
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  • Manager, Digital Design - Mixed-Signal…

    NVIDIA (Santa Clara, CA)
    Are you looking for a Digital Design Manager role? As a Senior Digital Design Manager in our Mixed-Signal High - Speed I/O SerDes group, you'll lead a team ... leadership role + Expertise in Verilog or SystemVerilog, logic design , and circuit modeling in RTL for...algorithms (FFE, DFE, CTLE, CDR, offset cancellation), understanding of high - speed SerDes I/O digital design ,… more
    NVIDIA (03/12/25)
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  • Design Engineer, Coherent High

    NVIDIA (Santa Clara, CA)
    NVIDIA is looking for a Design Engineer for our Coherent High Speed Interconnect team! For two decades, NVIDIA has pioneered visual computing, the art and ... Doing: + You will be working on architecture and design of our state-of-the-art high speed...will be useful. + Experience and knowledge in architecture, RTL design , performance analysis and power optimization.… more
    NVIDIA (05/02/25)
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  • Senior Design Engineer, Coherent…

    NVIDIA (Santa Clara, CA)
    NVIDIA is looking for a Senior Design Engineer for our Coherent High Speed Interconnect team! For two decades, NVIDIA has pioneered visual computing, the art ... Doing: + You will be working on architecture and design of our state-of-the-art high speed...PCIE , SerDes + Experience and knowledge in architecture, RTL design , performance analysis and power optimization.… more
    NVIDIA (04/22/25)
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  • Low Power ASIC Engineer (Next-Gen, High

    Qualcomm (San Diego, CA)
    …for development of next Generation, high performance, low power Memory Subsystem RTL Design , flows and methodology for high performance ASICs in ... in the entire low power, high performance ASIC/SoC design flows (micro-architecture, RTL design , verification, synthesis, timing/STA, UPF, CLP, LEC… more
    Qualcomm (02/15/25)
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  • Hardware Engineer, Design and Verification

    Google (Mountain View, CA)
    …Responsibilities: + High performance machine learning inference accelerator micro-architecture RTL design and verification. + Creation and steering of the ... verification planning and execution. + Creation of alignment between RTL design and design verification...of UVM libraries and testbench architectures. + Experience from design and integration of complex high - speed more
    Google (04/18/25)
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