• Implementation Timing / STA

    Qualcomm (Santa Clara, CA)
    …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design more
    Qualcomm (07/08/25)
    - Related Jobs
  • Principal Timing / STA Engineer

    Microsoft Corporation (Sunnyvale, CA)
    …semiconductor designs. + Collaborate with design , implementation , and physical design teams to define and drive timing constraints and methodology. + ... the Cloud infrastructure. We are looking for a **Principal Timing / STA Engineer** to join the team. **Responsibilities**...targets. + Work closely with cross-functional teams to resolve timing issues, optimize design performance, and meet… more
    Microsoft Corporation (07/11/25)
    - Related Jobs
  • Sr. SOC Design - STA , Hardware…

    Amazon (Sunnyvale, CA)
    …that is powering the latest generation of Echo devices is looking for a Senior SoC Design - STA Engineer to continue to innovate on behalf of our customers. We are ... Includes definition and development of signoff methodology and corresponding implementation solution * Flow for STA , Crosstalk...& Route and other local/remote teams to address the design challenges in the context of timing more
    Amazon (07/09/25)
    - Related Jobs
  • GPU STA Engineer (San Diego/Austin)

    Qualcomm (San Diego, CA)
    …+ Experience in static timing analysis, constraints and other physical implementation aspects + Familiar with digital flow design and industry standard ... tools used for RTL to GDS implementation + Good technical writing and communication skills in...debug across multi-mode, multi-voltage domain designs using industry standard timing tools + STA setup, convergence, reviews… more
    Qualcomm (07/08/25)
    - Related Jobs
  • CPU Physical Design Timing Engineer

    Qualcomm (San Diego, CA)
    …you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ... Design Timing Engineer,... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC, Innovous… more
    Qualcomm (06/10/25)
    - Related Jobs
  • ASIC Implementation Engineer…

    Meta (Sunnyvale, CA)
    …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints ... scripts and Methodology for all FE-tools including ( Synthesis, STA ) 6. Work closely with the Design ...supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing /congestion… more
    Meta (07/15/25)
    - Related Jobs
  • Senior ASIC Physical Design

    NVIDIA (Santa Clara, CA)
    …and/or full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, ... timing and power convergence, and ECO implementation . + Work in a cross-functional environment interacting with... Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints… more
    NVIDIA (06/30/25)
    - Related Jobs
  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …in Physical design / Timing . + Experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and ... as timing constraints, timing analysis, timing convergence, and ECO implementation . What we...multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg cell… more
    NVIDIA (06/10/25)
    - Related Jobs
  • Senior Static Timing Engineer, Google Cloud

    Google (Sunnyvale, CA)
    …about benefits at Google (https://careers.google.com/benefits/) . + Debug and resolve common Static Timing Analysis ( STA ) or design rule issues like ... + Experience writing, reviewing and verifying complex TCL constraints for static timing analysis. + Experience in extraction of design parameters, QoR… more
    Google (07/02/25)
    - Related Jobs
  • Senior High-Performance ASIC Timing

    NVIDIA (Santa Clara, CA)
    …or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation , and ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and...to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to… more
    NVIDIA (06/24/25)
    - Related Jobs