• Lead Post - Silicon

    NVIDIA (Santa Clara, CA)
    …today! What you'll be doing: + In this role, you will drive post - silicon bringup, characterization, and productization of the memory system for NIVIDIA's SOC ... NVIDIA is looking for a Lead DRAM Memory Subsystem Validation Engineer!...system software and firmware. + Develop tools to speedup post silicon bringup debug and characterization process.… more
    NVIDIA (08/08/25)
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  • Lead Post - Silicon

    NVIDIA (Santa Clara, CA)
    …+ In this role, you will manage and help lead post - silicon bringup, characterization, and productization of the memory system for NVIDIA's GPU products. ... We are seeking Lead Post - Silicon Validation Engineer...for customers internal and external, and DRAM vendors for silicon issues relating to memory . + Contribute… more
    NVIDIA (08/21/25)
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  • ASIC Engineer, Infra Silicon Pre/…

    Meta (Sunnyvale, CA)
    …within the Infrastructure organization. We are looking for individuals with experience in the Pre/ Post Silicon Validation to build and scale silicon for data ... solutions for Meta's data center applications. **Required Skills:** ASIC Engineer, Infra Silicon Pre/ Post Silicon Validation Responsibilities: 1. Work across… more
    Meta (08/01/25)
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  • Senior Post - Silicon Validation…

    NVIDIA (Santa Clara, CA)
    …plans. + Build supporting tools/script/infrastructure with relevant stakeholder teams. + Lead post - silicon bringup and support debug activities. ... pushing the boundaries to tackle complex challenges across diverse industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of… more
    NVIDIA (06/13/25)
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  • AR Subsystem Performance Architect, Reality Labs…

    Meta (Sunnyvale, CA)
    Lead Intellectual Property (IP) performance bottleneck analysis using traffic traces from pre/ post silicon platforms 5. Lead analysis and configuration of ... co-design 2. Own performance models for system interconnect, cache, memory hierarchy analysis 3. Own Subsystem Network on Chip...key performance metrics 13. 4+ years of expertise with post - silicon to pre- silicon correlation analysis… more
    Meta (08/01/25)
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  • System Memory Performance and Power…

    NVIDIA (Santa Clara, CA)
    …automotive, and professional solution markets. Prior experience in the lab with system-level post - silicon bring-up and debug is highly desired. What you'll be ... intelligence. Make the choice to join us today. NVIDIA Silicon Solutions Group is seeking a hardworking engineer to...doing: + Build roadmaps of memory system-level features to address low power, low noise,… more
    NVIDIA (06/15/25)
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  • Interconnect Productization Lead

    Amazon (Cupertino, CA)
    …software and signal integrity teams to productize the latest interconnect technology in both pre- silicon and post - silicon . Key job responsibilities * Gain a ... to build them with us! As an Interconnect Productization Lead , you will be responsible for ensuring the correct...functionality and performance. * Build verification environments for both pre- silicon and post - silicon . * Drive… more
    Amazon (07/29/25)
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  • Package Design Engineer

    Meta (Menlo Park, CA)
    …including substrate stackup/material selection, design guide implementation, layout review, and post -layout analysis 6. Lead pre-layout and post -layout ... focus for its ASIC packaging team to support the development of custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal… more
    Meta (08/01/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    …integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. + Your team will participate in the creation ... One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus...MBIST Architecture, MBIST Implementation and Verification. MBIST ATE bringup, post silicon debug and Diagnostics. + Prior… more
    Cisco (07/22/25)
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  • Lead ASIC DFT Engineer

    Google (Mountain View, CA)
    …architecture phase to design, front-end and back-end implementations, gate level simulations and post - silicon debug. Google is proud to be an equal opportunity ... scan insertion, Automatic Test Pattern Generation (ATPG), gate level simulations and silicon debug, low power designs, Built-In Self-Test (BIST), Joint Test Action… more
    Google (09/08/25)
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