• Low Power Design

    Qualcomm (San Diego, CA)
    … team to complete the IP design implementation. + Support SoC team to integrate low power / power management IP solution into wireless SoC chips and ... functional safety feature in automotive SoC product. + Create/Enhance low power methodologies covering entire design...cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design more
    Qualcomm (05/15/25)
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  • Sr. Staff Design Engineer ( Low

    Qualcomm (Santa Clara, CA)
    …ARM IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, ... IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, … more
    Qualcomm (04/09/25)
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  • Senior SoC Power Architect, Silicon

    Google (Mountain View, CA)
    …memory subsystems. + 5 years of experience in SoC power management or low power design / methodology . + Experience with Application-Specific Integrated ... power analysis. + 8 years of experience in SoC power management or low power design / methodology . + Experience in CPU power in mobile SoCs… more
    Google (05/07/25)
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  • Chipset Power Architect, Devices…

    Google (Mountain View, CA)
    …or equivalent practical experience. + 8 years of experience in power management or low power design / methodology . + Experience with low ... architecture and power optimization techniques (eg, multi Vth/ power /voltage domain design , clock gating, power gating, Dynamic Voltage Frequency Scaling… more
    Google (04/02/25)
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  • Power and Limits Management Architect

    Qualcomm (San Diego, CA)
    …and limits system + Familiar with UPF and power domain crossing + Experience in low power design methodology and clock domain crossing designs + ... for all. **Responsibilities** Candidate will be responsible for developing next generation power and limits system. With HPC, AI, and automotive system become so… more
    Qualcomm (03/28/25)
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  • Low Power ASIC Engineer (Next-Gen,…

    Qualcomm (San Diego, CA)
    …of next Generation, high performance, low power Memory Subsystem RTL Design , flows and methodology for high performance ASICs in sub-4nm process for ... low power designs. + Strong knowledge in the entire low power , high performance ASIC/SoC design flows (micro-architecture, RTL design ,… more
    Qualcomm (02/15/25)
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  • Physical Design Methodology

    Amazon (Cupertino, CA)
    …multiple vendor solutions and driving tool decisions. - Experience in high-performance, low - power physical design , and implementation techniques with ... today. Key job responsibilities - You will create and support innovative physical design methodology and CAD flows. - Develop cloud infrastructure to support… more
    Amazon (03/04/25)
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  • Design Methodology Engineer

    Qualcomm (San Diego, CA)
    … analysis concepts and on-hands experience with PTPX etc. ⦁ Sound conceptual understanding of low power design techniques like voltage/ power islands, ... and validate new flows and methodologies ⦁ Work on design power profiling and electromigration analysis ⦁...in languages such as Python, TCL, Perl ⦁ Strong methodology development background. Ability to drive solutions by creating… more
    Qualcomm (05/01/25)
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  • Senior Physical Design Methodology

    NVIDIA (Santa Clara, CA)
    … Engineering + Proven track record of PPA improvement on high performance and low power designs in advanced technology nodes + Strong understanding of physical ... with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all...files such as UPF, and use of FSDB/SAIFs for power optimization + Understanding of hierarchical design ,… more
    NVIDIA (02/20/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …understanding of mathematics/physics fundamentals of electrical design . + Clear understanding of low power design techniques such as multi VT, Clock ... and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the...drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the… more
    NVIDIA (04/18/25)
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