• Memory Control Design

    Qualcomm (San Diego, CA)
    …and data processing transformation to help create a smarter, connected future for all. QCT Memory Controller Design Team is looking for ASIC Design Engineers ... system such as CPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high...in QCT products. The candidate will work on architecture, design , and deployment of the Memory Controllers… more
    Qualcomm (03/05/25)
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  • ASIC Engineer , Memory Management…

    Meta (Sunnyvale, CA)
    …teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Memory Management Design Verification Responsibilities: 1. ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design more
    Meta (03/04/25)
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  • System Memory Performance and Power…

    NVIDIA (Santa Clara, CA)
    …use case analysis, and system level cost/benefit tradeoff. + Architect, design , and integrate memory system-level features, controllers, and policies ... today. NVIDIA Silicon Solutions Group is seeking a hardworking engineer to join a silicon HW team. As a...or equivalent experience. + 8+ years of experience in memory interface or subsystem architecture, design , and… more
    NVIDIA (03/16/25)
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  • Software Development Engineer , Nitro High…

    Amazon (Sunnyvale, CA)
    …assign projects based on what will help each team member develop into a better-rounded engineer and enable them to take on more complex tasks in the future 10017 ... and most feature-rich compute cloud. Nitro is AWS's ground-up design for virtualization at global scale built on a...or NVMe) and building compute infrastructure to support High Memory and High performance computing workloads. The Nitro High… more
    Amazon (04/29/25)
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  • Senior Mixed Signal Design Validation…

    NVIDIA (Santa Clara, CA)
    …teams, including Mixed signal design , PISI team, hardware, firmware, and Memory qualification engineer , to resolve issues and improve the performance for ... possible. We are looking for an experienced Mixed Signal Design Validation Engineer with a strong background...with a strong background in LPDDR, GDDR, and HBM memory technologies. As part of our high-speed mixed signal… more
    NVIDIA (04/11/25)
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  • Digital Design Engineer

    Meta (San Diego, CA)
    …SoCs that accelerate machine-learning and compute-vision workloads. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital ... Qualifications: 8. 3+ years of experience as a Hardware Design Engineer for production silicon shipped in...and optimization, including UPF flow. 16. Experience with NoC, memory control , DMA uArchitecture 17. Knowledge of… more
    Meta (05/01/25)
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  • Signal and Power Integrity Engineer

    Qualcomm (San Diego, CA)
    …to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital and/or analog), optimize, verify, ... package and IC designers to optimize the overall package design , including: + Utilizing experience and expertise in SRAM,...buffer operation, internal data bus pathways, refresh, power state control , etc. + Understanding of memory controller… more
    Qualcomm (03/21/25)
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  • ASIC Design Engineer , Cloud-Scale…

    Amazon (Cupertino, CA)
    … quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, area and ... of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia,… more
    Amazon (04/30/25)
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  • ASIC Engineer , Design

    Meta (Menlo Park, CA)
    …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC… more
    Meta (04/09/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...of these skills: Micro-architecture and RTL development for complex control and data path IPs, OR Experience in SoC… more
    Meta (03/12/25)
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