• Memory Sub - System…

    Qualcomm (San Diego, CA)
    …understand the HW u-architecture of the infrastructure components involved, the memory system and interconnect, identify performance bottlenecks; define ... and design of Platform infrastructure HW components such as Memory controllers, System cache, System ...Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.… more
    Qualcomm (06/06/25)
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  • Sr. ASIC Design Engineer, Cloud-Scale…

    Amazon (Cupertino, CA)
    …- Have familiarity with accelerator design, interconnects, DMAs, Memory sub - systems , CPU cores, SIMDs, debug and system level architectures - Have a ... and Japan, and customers across all industries. Custom SoCs ( System on Chip) live at the heart of AWS...rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies… more
    Amazon (06/14/25)
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  • Senior ASIC Design Verification Engineer…

    Qualcomm (San Diego, CA)
    …Engineer, you will work with Chip Architects to validate the concepts of core and sub - system level micro-architectures. You will work on a selected part of the ... you will plan, design, optimize, verify, and test electronic systems , validate digital/analog designs and develop a comprehensive validation/verification testbench… more
    Qualcomm (06/12/25)
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  • ASIC Verification Engineer

    Broadcom (San Jose, CA)
    …expertise with Interface IP designs. Beneficial areas would include High bandwidth memory (HBM) PHY / controller sub - systems , Ethernet/PCIE/CXL (Physical ... duties: + Functional verification of complex designs, especially external interfacing IPs/ memory controllers. + Responsible for all aspects of verification from test… more
    Broadcom (04/25/25)
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  • Lpddr Phy System Design Engineer

    Qualcomm (San Diego, CA)
    …DDR systems . **Preferred Qualifications** + Exposure to DDR, GDDR, and wide- memory systems . + Experience in latest process technology nodes and mixed-signal ... : + Drive the analysis and architectural ownership of LPDDR PHY systems . + Develop comprehensive system timing budgets, encompassing both on-die… more
    Qualcomm (07/02/25)
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  • Digital Design Engineer, Reality Labs Silicon AI…

    Meta (Sunnyvale, CA)
    …research silicon to demonstrate and integrate advanced IP and AI accelerators into SOC/ ASIC solutions to enable in- system testing and prototyping. The goal is ... our front-end and back-end digital design efforts at the IP and sub - system levels. From microarchitecture definition and RTL implementation to synthesis… more
    Meta (06/25/25)
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  • Processor RTL Design Engineer (Multiple Levels)

    Qualcomm (San Diego, CA)
    …architecture team to define micro-architecture for various blocks of Hexagon DSP core and sub - system + Develop RTL for multiple logic blocks of Hexagon DSP core ... and Automotive. This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the...and sub - system for SoC integration + Run various… more
    Qualcomm (07/17/25)
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  • Principal Software Engineer

    Microsoft Corporation (Mountain View, CA)
    …of a team driving the architecture, design and development of the various sub - systems including firmware development of low-level hardware interfaces and define ... give you an opportunity to design and architect the systems and servers of tomorrow that will scale in...flows for boot flows of ASIC . + You will be responsible for firmware level… more
    Microsoft Corporation (07/11/25)
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  • Senior Fabric Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …**Responsibilities** + Be part of a design team developing advanced components of the memory sub - system + Own multiple blocks within a complex, coherent ... 4+ years of experience in digital logic design for ASIC or FPGA + 4+ years of logic design...the IPs such as protocol bridges, PCIe, cache controllers, memory controllers and DDR, security engines. + Experience in… more
    Microsoft Corporation (07/12/25)
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  • Sr. CPU Architect, Project Kuiper

    Amazon (San Diego, CA)
    …7+ experience in performance architecture across CPUs, interconnect, high speed network I/O, and memory systems in SoCs with emphasis on power efficiency. - Must ... or granted asylum. A day in the life Be part of Project Kuiper's sub -team responsible for defining and implementing the digital chip SOCs for communications via Low… more
    Amazon (04/24/25)
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