- Google (Sunnyvale, CA)
- …of static timing analysis. + Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs ... field, or equivalent practical experience. + 7 years of experience in static timing (ie, full chip timing signoff ownership, constraint authoring and verification,… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. ... (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat and… more
- Qualcomm (San Diego, CA)
- …develop tools and methodologies for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading edge ... with spice, version-to-version validation. + Provide solutions to the Snapdragon design teams, analyze their requests, and address their requests through ticket… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical… more
- Meta (Sunnyvale, CA)
- …PPA (Power, Performance, and area) of the design . **Required Skills:** Silicon Physical Design Engineer Responsibilities: 1. Develop and own physical ... implementation of multi-hierarchy low-power ML Hardware design including physical -aware logic synthesis, floorplan, place and route, static timing analysis,… more
- SpaceX (Sunnyvale, CA)
- SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...+ Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Physical Design Engineer . NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... you'll be doing: + Responsible for all aspects of physical design and implementation of GPU and...assembly and P&R, timing closure. + Craft designs for static timing analysis, power and noise analysis and back-end… more
- Qualcomm (San Diego, CA)
- … physical -aware timing and IR drop ECO solutions ⦁ Collaborate closely with physical design and timing teams to drive methodologies to optimize power and ... methodologies in die-level IR drop, STA, and power. The engineer should be proficient in static timing...experience with Primetime or Tempus ⦁ In-depth knowledge of physical design , preferably but not limited to… more
- Google (Sunnyvale, CA)
- …a related field, or equivalent practical experience. + 7 years of physical design experience with industry-standard tools, languages, and methodologies relevant ... silicon interposer design and advanced packaging technologies. + Experience crafting physical design automation flows. In this role, you'll work to shape… more
- Capgemini (San Jose, CA)
- …_Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Mixed-Signal Design Verification Engineer_ **Location:** _CA-San ... **Job Role: Senior** **Mixed Signal DV Engineer ** **Job Location: San Jose CA** **Job description:**...This role will provide the ability to directly influence design related changes as required to meet functional specifications.… more
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